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c141-e110-02en mpg3xxxat disk drives product manual http://
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c141-e110-02en iii preface thi s m a nual descri bes t h e m pg3xxxat seri es, a 3.5-i nch hard di sk dri v e wi t h a built-in cont rol l e r t h at is com p atible with the ata interface. thi s m a nual expl ai ns, i n det a i l , how t o i n corporat e th e hard di sk dri v es i n t o user sy st em s. thi s m a nual assum e s t h at users have a basic knowl edge of hard di sk dri v es and t h ei r appl i cat i on i n com puter system s. thi s m a nual consi st s of t h e fol l owi ng si x chapt e rs: chapter 1 d evice overview chapter 2 d evice configuration chapter 3 installation conditions chapter 4 t heory of device operation chapter 5 interface chapter 6 operations in this m a nual, disk drives m a y be referred to as drives or devices.
iv c141-e110-02en conventi o ns for al ert messages thi s m a nual uses t h e fol l owi ng convent i ons t o show t h e al ert m e ssages. an al ert m e ssage consi st s of an al ert si gnal and al ert st at em ent s. the al ert si gnal consi st s of an al ert sy m bol and a si gnal word or just a si gnal word. the following are the alert signals and their m eanings: this indicates a hazardous situation likely to result in serious personal in ju ry if th e u ser d o e s n o t p e rfo rm th e p r o ced u r e co rrectly. this indicates a hazardous situation coul d resu lt in personal i n j u ry if the user does not perform the procedure correctly. this indicates a hazardous situation coul d resu lt in mi nor or moderat e personal i n j u ry if th e u ser d o e s n o t p e rfo rm th e p r o ced u r e co rrectly. th is al ert si gnal al so i ndi cat es t h at dam a ges t o t h e product or ot her propert y , may o ccu r if th e u ser d o e s n o t p e rfo rm th e p r o ced u r e co rrectly. thi s i ndi cat es i n form at i on t h at coul d hel p t h e user use t h e product m o re efficien tly. in t h e t e xt , t h e al ert si gnal i s cent e red, fol l owed bel ow by t h e i ndent ed m e ssage. a wi der l i n e space precedes and follows the alert m e ssage to show where the alert m e ssage begins and ends. the following is an exam ple: (exam p le) important ha (host adapter) consists of address decoder, driver, and receiver. ata i s an abbrevi at i on of "at at t a chment ". the di sk dri ve i s conformed t o t h e ata-5 i n t e rf ace th e m ain alert m essag es in th e tex t are also listed in th e im p o r tan t a l ert item s.
c141-e110-02en v liability ex ception "disk drive defects" refers to defects that involve adjustm ent, repair, or replacem ent. fujit su i s not l i a bl e for any ot her di sk dri v e defect s, such as t hose caused by user m i soperat i on or m i shandl i ng, i n appropri a t e operat i ng envi ronm ent s, defect s i n t h e power suppl y or cabl e , probl em s of t h e host syst em , or ot her causes out si de t h e di sk dri v e.
vi c141-e110-02en m anual organization mpg3xxxat disk drives product manual (c141-e110) ? device overview ? device configuration ? installation conditions ? theory of device operation ? interface ? operations m p g3xxxat disk drives m a intenance m anual (c141-f045) ? m a intenance and diagnosis ? removal and replacement procedure
c141-e110-02n vii contents page chapter 1 d evice overview ......................................................................................... 1 - 1 1.1 f eatures .................................................................................................................... ............ 1 - 1 1.1.1 f unctions and perform ance ................................................................................................. . 1 - 1 1.1.2 adaptability .............................................................................................................. ............ 1 - 2 1.1.3 interface ................................................................................................................. ............... 1 - 2 1.2 d evice specifications ....................................................................................................... .... 1 - 4 1.2.1 s pecifications sum m a ry .................................................................................................... .... 1 - 4 1.2.2 m odel and product num ber .................................................................................................. 1 - 5 1.3 p ower requirem e nts .......................................................................................................... ... 1 - 5 1.4 environm ental specifications ............................................................................................... 1 - 8 1.5 a coustic noise.............................................................................................................. ........ 1 - 8 1.6 s hock and vibration ......................................................................................................... .... 1 - 9 1.7 r eliability ................................................................................................................. ............ 1 - 9 1.8 error rate .................................................................................................................. ........... 1 - 10 1.9 m edia defects ............................................................................................................... ........ 1 - 10 chapter 2 d evice configuration ............................................................................ 2 - 1 2.1 d evice configuration ........................................................................................................ ... 2 - 1 2.2 s ystem configuration ........................................................................................................ ... 2 - 3 2.2.1 a ta interface ............................................................................................................. .......... 2 - 3 2.2.2 1 drive connection ........................................................................................................ ........ 2 - 3 2.2.3 2 drives connection ....................................................................................................... ........ 2 - 3 chapter 3 installation conditions ...................................................................... 3 - 1 3.1 d im ensions .................................................................................................................. ......... 3 - 1 3.2 h andling cautions ........................................................................................................... ..... 3 - 3 3.2.1 g eneral notes ............................................................................................................. ........... 3 - 3 3.2.2 installation .............................................................................................................. .............. 3 - 3 3.2.3 r ecom m e nded equipm ents ................................................................................................... 3 - 3 3.3 m ounting .................................................................................................................... .......... 3 - 4 3.4 c able connections ........................................................................................................... ..... 3 - 8 3.4.1 d evice connector .......................................................................................................... ........ 3 - 8
c141-e110-02en v iii 3.4.2 c able connector specifications ............................................................................................ . 3 - 9 3.4.3 d evice connection ......................................................................................................... ....... 3 - 9 3.4.4 p ower supply connector (cn1) ............................................................................................ 3 - 10 3.4.5 s ystem configuration for ultra dma ................................................................................... 3 - 1 0 3.5 jum per settings ............................................................................................................. ....... 3 - 13 3.5.1 location of setting jum pers ............................................................................................... ... 3 - 13 3.5.2 f actory default setting ................................................................................................... ....... 3 - 14 3.5.3 jum per configuration ...................................................................................................... ...... 3 - 14 chapter 4 t heory of device operation .............................................................. 4 - 1 4.1 outline ..................................................................................................................... ............. 4 - 1 4.2 s ubassem b lies ............................................................................................................... ........ 4 - 1 4.2.1 d isk ...................................................................................................................... ................ 4 - 1 4.2.2 h ead ...................................................................................................................... ................ 4 - 2 4.2.3 s pindle ................................................................................................................... ............... 4 - 3 4.2.4 a ctuator .................................................................................................................. .............. 4 - 3 4.2.5 a ir filter ................................................................................................................ ................ 4 - 3 4.3 c ircuit configuration ....................................................................................................... ..... 4 - 4 4.4 p ower-on sequence ........................................................................................................... ... 4 - 5 4.5 s elf-calibration ............................................................................................................ ......... 4 - 7 4.5.1 s elf-calibration contents ................................................................................................. ...... 4 - 7 4.5.2 execution tim ing of self-calibration ..................................................................................... 4 - 8 4.5.3 c om m a nd processing during self-calibration ....................................................................... 4 - 8 4.6 r ead/write circuit .......................................................................................................... ...... 4 - 9 4.6.1 r ead/write pream plifier (preamp) ...................................................................................... 4 - 9 4.6.2 w rite circuit ............................................................................................................. ............. 4 - 9 4.6.3 r ead circuit .............................................................................................................. ............. 4 - 9 4.6.4 tim e base generator circuit ............................................................................................... ... 4 - 10 4.7 s ervo control ............................................................................................................... ........ 4 - 12 4.7.1 s ervo control circuit ..................................................................................................... ........ 4 - 12 4.7.2 d ata-surface servo form at ................................................................................................. ... 4 - 15 4.7.3 s ervo fram e form at ........................................................................................................ ....... 4 - 16 4.7.4 a ctuator m o tor control .................................................................................................... ..... 4 - 17 4.7.5 s pindle m o tor control ..................................................................................................... ...... 4 - 18
c141-e110-02n ix chapter 5 i nterface ........................................................................................................ 5 - 1 5.1 p hysical interface .......................................................................................................... ....... 5 - 2 5.1.1 interface signals ......................................................................................................... ........... 5 - 2 5.1.2 s ignal assignm ent on the connector ..................................................................................... 5 - 3 5.2 logical interface ........................................................................................................... ........ 5 - 6 5.2.1 i/o registers ............................................................................................................. ............. 5 - 6 5.2.2 c om m a nd block registers ................................................................................................... .. 5 - 8 5.2.3 c ontrol block registers ................................................................................................... ...... 5 - 13 5.3 host com m a nds ............................................................................................................... .... 5 - 13 5.3.1 c om m a nd code and param e ters ............................................................................................ 5 - 14 5.3.2 c om m a nd descriptions ...................................................................................................... ... 5 - 16 5.3.3 error posting ............................................................................................................. ............ 5 - 75 5.4 c om m a nd protocol ............................................................................................................ ... 5 - 76 5.4.1 d ata transferring com m a nds from device to host ................................................................. 5 - 76 5.4.2 d ata transferring com m a nds from host to device ................................................................. 5 - 78 5.4.3 c om m a nds wi t hout dat a t ransfer .......................................................................................... 5 - 80 5.4.4 o ther com m a nds ............................................................................................................ ....... 5 - 81 5.4.5 d ma data transfer com m a nds .............................................................................................. 5 - 81 5.5 u ltra dma feature set ....................................................................................................... . 5 - 83 5.5.1 overview .................................................................................................................. ............ 5 - 83 5.5.2 p hases of operation ....................................................................................................... ........ 5 - 84 5.5.3 u ltra dma data in com m a nds .............................................................................................. 5 - 84 5.5.3.1 initiating an ultra dma data in burst .................................................................................. 5 - 84 5.5.3.2 the data in transfer ................................................................................................... ............ 5 - 85 5.5.3.3 pausing an ultra dma data in burst .................................................................................... 5 - 85 5.5.3.4 term inating an ultra dma data in burst ............................................................................. 5 - 86 5.5.4 ultra dma data out com m a nds ............................................................................................ 5 - 88 5.5.4.1 initiating an ultra dma data out burst ................................................................................ 5 - 88 5.5.4.2 the data out transfer .................................................................................................. ........... 5 - 89 5.5.4.3 pausing an ultra dma data out burst .................................................................................. 5 - 89 5.5.4.4 term inating an ultra dma data out burst ........................................................................... 5 - 9 0 5.5.5 ultra dma crc rules ...................................................................................................... .... 5 - 92 5.5.6 series term ination required for ultra dma .......................................................................... 5 - 93 5.6 tim i ng ..................................................................................................................... ............. 5 - 94 5.6.1 pio data transfer ........................................................................................................ ........... 5 - 94 5.6.2 multiword data transfer .................................................................................................. ...... 5 - 95
c141-e110-02en x 5.6.3 ultra dma data transfer .................................................................................................. ..... 5 - 96 5.6.3.1 initiating an ultra dma data in burst .................................................................................. 5 - 96 5.6.3.2 ultra dma data burst tim ing requirem e nts .......................................................................... 5 - 9 7 5.6.3.3 sustained ultra dma data in burst ...................................................................................... 5 - 100 5.6.3.4 host pausing an ultra dma data in burst ............................................................................ 5 - 101 5.6.3.5 device terminating an ultra dma data in burst .................................................................. 5 - 102 5.6.3.6 host term inating an ultra dma data in burst ...................................................................... 5 - 10 3 5.6.3.7 initiating an ultra dma data out burst ................................................................................ 5 - 104 5.6.3.8 sustained ultra dma data out burst .................................................................................... 5 - 105 5.6.3.9 device pausing an ultra dma data out burst ...................................................................... 5 - 106 5.6.3.10 host term inating an ultra dma data out burst .................................................................... 5 - 107 5.6.3.11 device terminating an ultra dma data in burst .................................................................. 5 - 108 5.6.4 power-on and reset ....................................................................................................... ........ 5 - 109 chapter 6 operations ..................................................................................................... 6 - 1 6.1 devi ce response t o t h e reset ............................................................................................... 6 - 1 6.1.1 response t o power-on ..................................................................................................... ..... 6 - 2 6.1.2 response t o hardware reset ............................................................................................... ... 6 - 3 6.1.3 response t o soft ware reset ............................................................................................... .... 6 - 4 6.1.4 response t o di agnost i c com m a nd ......................................................................................... 6 - 5 6.2 address transl at i o n ........................................................................................................ ...... 6 - 6 6.2.1 default param e ters ....................................................................................................... ......... 6 - 6 6.2.2 logical address .......................................................................................................... ........... 6 - 7 6.3 power save ................................................................................................................. .......... 6 - 8 6.3.1 power save m ode .......................................................................................................... ........ 6 - 8 6.3.2 power com m a nds ........................................................................................................... ....... 6 - 10 6.4 defect managem e nt .......................................................................................................... .... 6 - 10 6.4.1 spare area ............................................................................................................... .............. 6 - 11 6.4.2 alternating defective sectors ............................................................................................ .... 6 - 11 6.5 read-ahead cache ........................................................................................................... .... 6 - 13 6.5.1 data buffer configuration ................................................................................................ ..... 6 - 13 6.5.2 caching operation ........................................................................................................ ......... 6 - 14 6.5.3 usage of read segm ent .................................................................................................... ...... 6 - 15 6.6 w rite cache ................................................................................................................ .......... 6 - 20
c141-e110-02n xi figures page 1.1 c urrent fl uct u at i on (ty p .) when power i s t u rned on ............................................................ 1 - 7 2.1 d isk drive outerview ........................................................................................................ .... 2 - 1 2.2 1 drive system configuration ................................................................................................ 2 - 3 2.3 2 drives configuration ...................................................................................................... ..... 2 - 3 3.1 d im ensions .................................................................................................................. ......... 3 - 2 3.2 h andling cautions ........................................................................................................... ...... 3 - 3 3.3 d irection ................................................................................................................... ............ 3 - 4 3.4 lim itation of side-m ounting ................................................................................................. 3 - 5 3.5 m ounting fram e structure .................................................................................................... . 3 - 5 3.6 surface temp erature m easurem ent points ............................................................................. 3 - 6 3.7 s ervice area ................................................................................................................ .......... 3 - 7 3.8 c onnector locations ......................................................................................................... ..... 3 - 8 3.9 c able connections ........................................................................................................... ...... 3 - 9 3.10 power supply connector pins (cn1) ..................................................................................... 3 - 1 0 3.11 cable configuration ........................................................................................................ ...... 3 - 11 3.12 cable ty p e det ect i on usi ng cblid- si gnal (host sensing the condition of the cblid- signal) .............................................................. 3 - 12 3.13 cable ty p e det ect i on usi ng identify device dat a (device sensing the condition of the cblid- signal) .......................................................... 3 - 12 3.14 jum p er location ............................................................................................................ ........ 3 - 13 3.15 factory default setting .................................................................................................... ...... 3 - 14 3.16 jum p er setting of m a ster or slave device .............................................................................. 3 - 1 4 3.17 jum p er setting of cable select ............................................................................................. 3 - 15 3.18 exam ple (1) of cable select ................................................................................................ . 3 - 15 3.19 exam ple (2) of cable select ................................................................................................ . 3 - 15 4.1 h ead structure .............................................................................................................. ......... 4 - 2 4.2 m pg3xxxat bl ock di agram ................................................................................................ 4 - 5 4.3 p ower-on operation sequence ............................................................................................... 4 - 6 4.4 b lock diagram of servo control circuit ................................................................................. 4 - 1 2 4.5 p hysical sector servo configuration on disk surface ............................................................. 4 - 14 4.6 126 servo fram e s in each track............................................................................................. 4 - 16 5.1 execution exam ple of read multiple com m and .......................................................... 5 - 19 5.2 r ead sector(s) com m a nd protocol ....................................................................................... 5 - 77
c141-e110-02en xi i 5.3 p rotocol for com m a nd abort ................................................................................................. 5 - 78 5.4 w rite sector(s) com m a nd protocol ............................................................................. 5 - 79 5.5 p rot o col for t h e com m a nd execut i on wi t hout dat a t ransfer .................................................. 5 - 80 5.6 norm a l dma data transfer ................................................................................................... 5 - 82 5.7 u l t ra dm a t erm i n at i on wi t h pul l -up or pul l -down .............................................................. 5 - 93 5.8 p io data transfer tim ing .................................................................................................... ... 5 - 94 5.9 m ultiword dma data transfer tim ing (m ode 2) ................................................................... 5 - 95 5.10 initiating an ultra dma data in burst .................................................................................. 5 - 96 5.11 sustained ultra dma data in burst ...................................................................................... 5 - 100 5.12 host pausing an ultra dma data in burst ............................................................................ 5 - 101 5.13 device terminating an ultra dma data in burst .................................................................. 5 - 102 5.14 host term inating an ultra dma data in burst ...................................................................... 5 - 103 5.15 initiating an ultra dma data out burst ................................................................................ 5 - 1 04 5.16 sustained ultra dma data out burst .................................................................................... 5 - 1 05 5.17 device pausing an ultra dma data out burst ...................................................................... 5 - 106 5.18 host term inating an ultra dma data out burst .................................................................... 5 - 107 5.19 device terminating an ultra dma data out burst ................................................................ 5 - 108 5.20 power-on reset tim i ng ...................................................................................................... .. 5 - 109 6.1 response t o power-on ....................................................................................................... ... 6 - 2 6.2 response t o hardware reset ................................................................................................. . 6 - 3 6.3 response t o soft ware reset ................................................................................................. .. 6 - 4 6.4 response t o di agnost i c com m a nd ......................................................................................... 6 - 5 6.5 address t ransl at i on (exam p l e i n chs m ode) ....................................................................... 6 - 7 6.6 address t ransl at i on (exam p l e i n lba m ode) ....................................................................... 6 - 8 6.7 sector slip processing ..................................................................................................... ...... 6 - 11 6.8 alternate cylinder assignm ent .............................................................................................. 6 - 12 6.9 data buffer configuration .................................................................................................. ... 6 - 13
c141-e110-02n xiii tables page 1.1 s pecifications .............................................................................................................. ......... 1 - 4 1.2 m odel nam e s and product num bers ...................................................................................... 1 - 5 1.3 c urrent and power di ssi pat i o n .............................................................................................. 1 - 6 1.4 environm ental specifications ............................................................................................... 1 - 8 1.5 a coustic noise specification ................................................................................................ . 1 - 8 1.6 s hock and vibration specification......................................................................................... 1 - 9 3.1 surface temp erature m easurem ent points and standard values............................................. 3 - 6 3.2 c able connector specifications ............................................................................................. 3 - 9 4.1 transfer rate of each zone .................................................................................................. .. 4 - 11 5.1 interface signals ........................................................................................................... ......... 5 - 2 5.2 signal assignm ent on the interface connector ...................................................................... 5 - 3 5.3 i/o registers ............................................................................................................... ........... 5 - 7 5.4 c om m a nd code and param e ters ............................................................................................ 5 - 1 4 5.5 inform a tion to be read by identify device com m and .................................................. 5 - 29 5.6 features register values and settable m odes ......................................................................... 5 - 37 5.7 d i a gnost i c code ............................................................................................................. ....... 5 - 41 5.8 f eatures register values (subcom m a nds) and functions ...................................................... 5 - 51 5.9 d evice attribute data structure ............................................................................................. . 5 - 54 5.10 w a rranty failure threshold data structure ............................................................................. 5 - 5 5 5.11 error l oggi ng dat a st ruct ure ............................................................................................... ... 5 - 59 5.12 contents of security password .............................................................................................. 5 - 62 5.13 contents of security set passw ord data ................................................................. 5 - 67 5 . 1 4 relatio n sh i p b etw een co m b in ation o f id en tifier an d secu rity lev el, and operation of the lock function ........................................................................................ 5 - 6 7 5.15 com m a nd code and param e ters ............................................................................................ 5 - 75 5.16 recom m e nded series term ination for ultra dma ................................................................ 5 - 93 5.17 ultra dma data burst tim ing requirem e nts .......................................................................... 5 - 97 5.18 ultra dma sender and recipient tim ing requireme nts ......................................................... 5 -99 6.1 d efault param e ters .......................................................................................................... ...... 6 - 6
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c141-e110-02en 1 - 1 chapter 1 device over view 1.1 features 1.2 d evice specifications 1.3 power requirements 1.4 e nvironmental specifications 1.5 a cousti c noi se 1.6 shock and vibration 1 . 7 r elia bility 1.8 e rror rate 1.9 m edia defects overvi e w and feat ures are descri bed i n t h i s chapt e r, and speci fi cat i ons and power requi rem e nt are descri bed. the mpg3xxxat series are a 3.5-inch hard disk drive with a built-in ata controller. the disk drive is com p act and reliable. 1.1 features 1.1.1 functions and performance (1) c om pact the di sk dri v e has 1 or 2 di sks of 95 m m (3.5 i n ches) di am et er, and i t s hei ght i s 26.1 m m (1 i n ch). (2) large capacity the di sk dri v e can record up t o 20.49 gb (form at t e d) on one di sk usi ng t h e 48/ 51 cc2eprm l recordi ng m e t hod and 15 recordi ng zone t echnol ogy . the m p g3xxxat seri es have a form at t e d cap acity of 1 0 . 2 4 g b to 4 0 . 9 9 g b resp ectiv ely. (3) h igh-speed transfer rate the di sk dri v e has an i n t e rnal dat a rat e up t o 49.8 m b / s. the di sk dri v e support s an ext e rnal dat a rat e up t o 16.6 m b / s (pio m ode 4, dm a m ode 2), 66.6 m b / s (ul t ra dm a m ode 4) or 100 m b / s (ul t ra dm a m ode 5).
c141-e110-02en 1 - 2 (4) average posi t i oni ng t i m e u se o f a ro tary v o i ce co il m o to r in th e h ead p o sition i n g m ech an ism g r eatly in creases th e posi t i oni ng speed. the average posi t i oni ng t i m e i s 9.5 m s (at read). 1 . 1 . 2 a da pta b ility (1) p ower save m ode the power save m ode feat ure for i d l e operat i on, st and by and sl eep m odes m a kes t h e di sk dri v e i d eal for appl i cat i ons where power consum pt i on i s a fact or. (2) w ide tem p erature range the di sk dri v e can be used over a wi de te m p erature range (5c t o 55c). (3) low noi se and vi brat i o n in ready st at us, t h e noi se of t h e di sk dri v e i s onl y about 3.4 bel s (m pg3409at, ty pi cal sound power per iso7779 and iso9296). 1.1.3 interface (1 ) c o n n ectio n to in terface w ith the built-in ata interface controller, the disk drive can be connected to an ata interface of a personal com put er. (2) d ata buffer the di sk dri v e uses a 512-kb or 2-m b dat a buffer t o t r ansfer dat a bet w een t h e host and t h e di sk me d i a . in com b ination with the read-ahead cache system described in item (3) and the write cache described in item (6), the buffer contributes to efficient i/o processing. (3) r ead-ahead cache system a f ter th e ex ecu tio n o f a d i sk read co m m an d , th e d i sk d r iv e au to m atically read s th e su b seq u en t data block and writes it to the data buffer (read ahead operation). this cache system enables fast data access. the next disk read com m a nd would norm a lly cause another disk access. but, if the read ahead dat a corresponds t o t h e dat a request ed by t h e next read com m a nd, t h e dat a i n t h e buffer can be transferred instead.
c141-e110-02en 1 - 3 (4) m aster/slave the disk drive can be connected to ata interface as daisy chain configuration. drive 0 is a m a ster device, drive 1 is a slave device. (5) error correction and retry by ecc if a recoverable error occurs, the disk drive itself attem p ts error recovery. the 42 bytes ecc has im proved buffer error correction for correctable data errors. (6) w rite cache w h en the disk drive receives a write com m and, the disk drive posts the com m a nd com p letion at com p l e t i on of t ransferri ng dat a t o t h e dat a buffer com p l e t i on of wri t i ng t o t h e di sk m e di a. thi s feature reduces the access tim e at writing.
c141-e110-02en 1 - 4 1.2 d evice specifications 1.2.1 specifications summary table 1.1 shows t h e speci fi cat i ons of t h e disk dri v e. table 1.1 specifications m pg3153at m pg3307at m pg3102at m pg3204at m pg3409at form atted capacity (*1) 15.37 gb 30.74 gb 10.24 gb 20.49 gb 40.99 gb n umber of disks 12112 num b er of heads 24124 num b er of cylinders (user + alternate & sa) 28, 928 + 698 30,784 + 769 bytes per sector 512 recor ding method 48/51 cc2eprml t rack density 31,000 tpi 33,000 tpi b it density 388,716 bpi 478,415 bpi rotational speed 5400 rpm average latency 5.56 m s positioning tim e (fast) ? min i m u m ? average ? max i m u m (read) 1.0 m s typical, (write) 1.2 ms typical (read) 9.5 ms typical, (write) 10.5 ms typical (read) 17 ms typical, (write) 18 ms typical positioning time (slow) ? min i m u m ? average ? max i m u m (read) 1.0 m s typical, (write) 1.2 m s typical (read) 12 m s typical, (write) 13 m s typical (read) 20 m s typical, (write) 21 m s typical start/stop time ? start (0 rpm to drive read) ? stop (at power down) typical: 8 sec. maxim u m : 15 sec. typical: 20 sec. maxim u m : 30 sec. interface ata-5 ( m a xim u m cable length: 0. 46 m [18 inch] ) data transfer rate ? to /fro m med i a ? to/from host 22. 7 to 38. 6 m b /s 16. 6 m b /s m a x. ( bur st pi o m ode4, bur st dm a m ode2) 66. 6 m b/s m a x. ( bur st ultr a dm a m ode4) , 100. 0 m b/s m a x. ( bur st ultr a dm a m ode5) 27. 5 to 49. 8 m b /s 16. 6 m b/s m a x. ( bur st pi o m ode4, bur st dm a m ode2) 66. 6 m b/s m a x. ( bur st ultr a dm a m ode4) , 100. 0 m b/s m a x. ( bur st ultr a dm a m ode5) data buffer 512 kb (option: 2,048 kb) physical dim ensions (height w i dth depth) 26. 1 m m m a x. 101. 6 m m 146. 0 m m ( 1 . 03 m a x. 4. 0 5.75) weight 600 g or less *1: capacity under the lba m ode. under the chs m ode (norm al bios specification), form atted capacity, num ber of cylinders, number of heads, and number of sectors are as follows.
c141-e110-02en 1 - 5 chs param eter model f orm atted capacity no. of cylinder n o. of heads no. of sectors m pg3102at 10, 248 m b 16, 383 16 63 m pg3153at 15, 371 m b 16, 383 16 63 m pg3204at 20, 496 m b 16, 383 16 63 m pg3307at 30, 743 m b 16, 383 16 63 m pg3409at 40, 992 m b 16, 383 16 63 1.2.2 m odel and product number tabl e 1.2 l i s t s t h e m odel nam e s and product num bers. table 1.2 m odel names and product numbers m odel nam e capaci t y (user area) mo u n tin g screw order no. rem a rks m p g3102at 10.24 gb no. 6-32unc ca05761-b511 512 kb data buffer m p g3153at 15.37 gb no. 6-32unc ca05761-b323 512 kb data buffer m p g3204at 20.49 gb no. 6-32unc ca05761-b521 512 kb data buffer m p g3307at 30.74 gb no. 6-32unc ca05761-b343 2,048 kb data buffer m p g3409at 40.99 gb no. 6-32unc ca05761-b542 2,048 kb data buffer 1.3 power requirements (1) i nput vol t a ge + 5 v 5 % + 12 v 8 % (2) r i pple +12 v + 5 v m aximum 200 mv (peak to peak) 100 mv (peak to peak) frequency dc to 1 mhz dc to 1 mhz (3) c urrent requi rem e nt s and power di ssi pat i o n tabl e 1.3 lists the current and power dissipation.
c141-e110-02en 1 - 6 table 1.3 c urrent and power dissipation typical rms current (*1) [ m a] +12 v +5 v m odel m pg3102at m pg3153at m pg3204at all models MPG3102AT mpg3153at mpg3204at spin up 1600 1800 peak 1600 1800 peak 570 600 peak 22.1 22.1 idle (ready) (*3) 230 270 460 5.1 5.5 r/w (on track) (*4) 300 330 460 5.9 6.3 seek (random ) (*5) seek/w/r 430 450 460 7.5 7.7 standby 18 18 120 0.8 0.8 sleep 18 18 120 0.8 0.8 m odel m pg3153at m pg3102at m pg3204at mpg3307at mpg3409at energy efficiency (rank)(*6)[watt/gb] 0.332 (a) 0.249 (a) 0.179 (b) 0.134 (b) *1 current is typical rm s except for spin up. *2 power requirem e nts reflect nom inal values for +12v and +5v power. *3 idle m ode is in effect when the drive is not reading, writing, seeking, or executing any com m a nds. a portion of the r/w circuitry is powered down, the spindle m o tor is up to speed and the drive ready condition exists. *4 r/w m ode is defined as 50% read operations and 50% write operations on a single physical track. *5 seek/w/r m ode is defined as 33% seek operations, 33% write operations and 33% read operations. *6 energy efficiency based on the law concerning the rational use of energy indicates the value obtained by dividing power consum ption by the storage capacity. (japan only) typical power (*2) [watts] mode of operation mpg3307at mpg3409at mpg3307at mpg3409at
c141-e110-02en 1 - 7 (4) c urrent fl uct u at i on (ty p .) when power i s t u rned on note: m a xi m u m current i s 1.8 a. figure 1.1 c urrent fluctuation (typ.) when power is turned on (5) p ower on/ off sequence the vol t a ge det ect or ci rcui t m oni t o rs +5 v and +12 v. the ci rcui t does not al l ow a wri t e si gnal i f either voltage is abnormal. this prevents data from being destroyed and eliminates the need to be concerned with the power on/off sequence. +5vdc (0.5a/ di v) 0.0 0.0 0.5 1.0 [a] 1.5 [a] 0.5 1 0 +12vdc (0.5a/ di v) 3 25 4 [ seconds] 6
c141-e110-02en 1 - 8 1.4 e nvironmental specifications table 1.4 l i st s t h e envi ronm ent a l speci fi cat i ons. table 1.4 e nvironmental specifications tem p erature ? o p eratin g ? non-operat i n g ? th erm al g r ad ien t 5c to 55c (am b ient) 5c to 60c (disk enclosure surface) C40c t o 60c 20c/ hour or l e ss humidity ? o p eratin g ? non-operat i n g ? max i m u m w e t bu lb 8% t o 80%rh (non-condensi ng) 5% t o 85%rh (non-condensi ng) 29c altitude (relative to sea lev e l) ? o p eratin g ? non-operat i n g C60 t o 3,000 m (C200 t o 10,000 ft ) C60 t o 12,000 m (C200 t o 40,000 ft ) 1.5 a cousti c noi se tabl e 1.5 l i s t s t h e acoust i c noise specification. table 1.5 acoustic noise specification model MPG3102AT mpg3153at mpg3204at mpg3307at mpg3409at idle mode (drive ready) 3.3 bels 3.4 bels 3.1 bels seek mode (random) 3 .6 bels 3.9 bels 3.6 bels idle mode (drive ready) 28 dba 29 dba 25 dba seek mode (random) 31 dba 34 dba 31 dba sound power per iso 7779 and iso9296 (ty p ical at 1m ) sound pressure (ty p ical at 1m )
c141-e110-02en 1 - 9 1.6 shock and vibration table 1.6 l i st s t h e shock and vi brati on speci fi cat i on. table 1.6 shock and vibration specification vi brat i on (swept si ne, one oct a ve per m i nut e) ? o p eratin g ? non-operat i n g 4.9m / s 2 (0.5 g0-p); 5 t o 300 hz (wi t hout non-recovered errors) 39.2m/ s 2 (4.0 g0-p); 5 t o 400 hz (no dam a ge) shock (hal f-si n e pul se, operat i ng) ? 2 m s durat i o n 392m/s 2 (40g) (without non-recovered error) shock (hal f-si n e pul se, non-operat i ng) ? 2 m s durat i o n 2940m/s 2 (300g) (typical, no damage) 1 . 7 r elia bility (1) m ean tim e between failures (mtbf) the m ean t i m e bet w een fai l u res (m tbf) i s 500,000 poh (power on hours) or m o re (operat i on: 24 hours/ day , 7 day s / w eek). thi s does not i n cl ude fai l u res occurri ng duri ng t h e fi rst t h ree m ont hs aft e r i n st al l a t i on. m t bf i s defi ned as fol l ows: mtbf= ( h ) "disk drive defects" refers to defects that involve repair, readjustm ent, or replacem ent. disk drive defect s do not i n cl ude fai l u res caused by ext e rnal fact ors, such as dam a ge caused by handl i ng, inappropriate operating environm ents, defects in the power supply host system , or interface cable. (2) m ean tim e to repair (mttr) th e m ean tim e to rep air (mttr) is 3 0 m i n u t es o r less, if rep aired b y a sp ecialist m ain ten an ce st a f f me mb e r . (3) c ss cycle the num ber of css m u st be l e ss t h an 50,000. to tal o p e ratio n tim e in all field s num ber of devi ce fai l u re i n all fiel ds
c141-e110-02en 1 - 10 (4) s ervice life in si t u at i ons where m a nagem e nt and handl i ng are correct , t h e di sk dri v e requi res no overhaul for five years when the de surface tem p erature is less than 48c. w h en the de surface tem p erature exceeds 48c, the disk drives requires no overhaul for five years or 20,000 hours of operation, whi chever occurs fi rst . refer t o i t e m (3) i n subsect i on 3.3 for t h e m easurem ent poi nt of t h e de surface tem p erature. (5) d at a assurance i n t h e event of power fai l u re ex cep t fo r th e d ata b l o ck b ein g w r itten to , th e d ata o n th e d i sk m ed i a is assu red in th e ev en t o f an y power supply abnorm a lities. this does not include power supply abnorm a lities during disk m e dia in itializatio n (fo rm attin g ) o r p r o cessin g o f d efects (altern ative b l o ck assig n m en t). 1.8 e rror rate known defect s, for whi ch al t e rnati v e bl ocks can be assi gned, are not i n cl uded i n t h e error rat e count below. it is assum e d that the data blocks to be accessed are evenly distributed on the disk me d i a . (1) unrecoverable read error read errors t h at cannot be recovered by read ret r i e s wi t hout user' s ret r y and ecc correct i ons shal l occur no m o re t h an 10 t i m es when readi ng dat a of 10 15 bits. read retries are executed according to the disk drive's error recovery procedure, and include read retries accom p anying head offset operat i ons. (2) p osi t i oni ng error posit i oni ng (seek) errors t h at can be recovered by one ret r y shal l occur no m o re t h an 10 t i m es i n 10 7 seek operat i ons. 1.9 m edia defects defective sectors are replaced with alternates when the disk is form atted prior to shipm e nt from the factory (low level form at). thus, the host sees a defect-free device. alternate sectors are autom a tically accessed by the disk drive. the user need not be concerned with access to alternate sectors. chapt e r 6 descri bes t h e l ow le vel form at at shippi ng.
c141-e110-02en 2 - 1 chapter 2 device configura tion 2.1 d evi ce confi gurati on 2.2 s ystem confi gurati on 2.1 d evi ce confi gurati on fi gure 2.1 shows t h e di sk dri v e. the di sk dri v e consi st s of a di sk encl osure (de), read/ w ri t e pream pl i f i e r, and cont rol l e r pca. the di sk encl osure cont ai ns t h e di sk m e di a, heads, spi ndl e m o to rs actuato rs, an d a circu l ating air filter. figure 2.1 disk drive outerview
c141-e110-02en 2 - 2 (1) d isk the out er di am et er of t h e di sk i s 95 m m . the i nner di am et er i s 25 m m . the num ber of di sks used vari es wi t h t h e m odel, as descri bed bel ow. the di sks are rat e d at over 50,000 st art / st o p operat i ons. m p g3102at, m p g3153at, m p g3204at: 1 di sk m p g3307at, m p g3409at: 2 di sks (2) h ead the heads are of the contact start/stop (css) type. the head touches the disk surface while the d i sk is n o t ro tatin g an d au to m atically lifts w h en th e d i sk starts. (3) s pi ndl e m o t o r the di sks are rot a t e d by a di rect dri v e hal l - l e ss dc m o t o r. (4) a ctuator the act uat o r uses a revol vi ng voi ce coi l m o t o r (vcm ) st ructure whi ch consum es l ow power and g en erates v ery little h eat. th e h ead assem b ly at th e tip o f th e actu ato r arm is co n t ro lled an d posi t i oned by feedback of t h e servo i n form at i on read by t h e read/ w ri t e head. if t h e power i s not on or i f t h e spi ndl e m o t o r i s st opped, t h e head assem b l y st ay s i n t h e speci fi c css zone on t h e di sk and is fixed by a m echanical lock. (5) a ir circulation system the disk enclosure (de) is sealed to prevent dust and dirt from entering. the disk enclosure features a cl osed l oop ai r ci rculat i on sy st em t h at rel i e s on t h e bl ower effect of t h e rot a t i ng di sk. this system continuously circulates the air through the recirculation filter to m a intain the cleanliness of the air in the disk enclosure. (6) r ead/write circuit th e read/w rite circu it u ses a lsi ch ip fo r th e read /w rite p r eam p lifier. it im p r o v es d ata reliab ility by prevent i ng errors caused by ext e rnal noi se. (7) c ontroller circuit th e co n t ro ller circu it co n sists o f an lsi ch ip to im p r o v e reliab ility. th e h i g h - sp eed m i croprocessor uni t (mpu) achi e ves a hi gh-perform ance at cont rol l e r.
c141-e110-02en 2 - 3 2.2 s ystem confi gurati on 2.2.1 a ta i nterface figures 2.2 and 2.3 show the ata interface system configuration. the drive has a 40-pin pc at interface connector and supports the pio transfer till 16.6 mb/s (pio m ode 4), the dma transfer till 1 6 . 6 mb/s (mu ltiwo r d d m a m o d e 2 ), th e u ltra d m a tran sfer till 6 6 . 6 mb/s (u ltra d m a m ode 4), and the ultra dma transfer till 100 mb/s (ultra dma m ode 5). 2.2.2 1 drive connection ha ( h o s t ad ap to r ) at b u s (host interface) host di sk d r i v e a ta in te r f ac e figure 2.2 1 drive system configuration 2.2.3 2 drives connection ha ( h o s t ad ap to r ) at b u s (host interface) host di sk d r i v e # 0 a ta in te r f ac e disk dri v e # 1 note: when t h e drive that is not conformed to ata is connected to the disk drive is above configuration, the operation is not guaranteed. figure 2.3 2 drives configuration
c141-e110-02en 2 - 4 important ha (host adaptor) consists of address decoder, driver, and receiver. ata i s an abbrevi at i on of "at at t a chment ". the di sk dri ve i s conformed t o t h e ata-5 i n t e rf ace. at hi gh speed dat a t ransf e r ( pio mode 3, mode 4, dma mode 2, ul t ra dma mode 4, or ul t ra dma mode 5) , occurrence of ri ngi ng or crosst al k of t h e si gnal l i n es ( at bus) bet w een t h e ha and t h e di sk dri v e m a y b e a g rea t ca u se o f th e o b stru c tio n o f system relia b ility. th u s, it is necessary t hat t h e capaci t ance of t h e si gnal l i n es i n cl udi ng t h e ha and cable does not exceed the ata-3 and ata-4 standard, and the cable l e ngt h bet w een t h e ha and t h e di sk dri ve shoul d be as short as possi bl e.
c141-e110-02en 3 - 1 chapter 3 inst alla tion conditions 3.1 d i mensi ons 3.2 handl i n g cauti ons 3.3 mounti n g 3.4 cable connecti o ns 3.5 jumper settings 3.1 d i mensi ons figure 3.1 illustrates the dim e nsions of the disk drive and positions of the m ounting screw holes. al l di m e nsi ons are i n m m .
c141-e110-02en 3 - 2 figure 3.1 d imensions
c141-e110-02en 3 - 3 3.2 h andl i n g cauti ons pl ease keep t h e fol l owi ng caut i ons, and handl e th e hdd under t h e safet y envi ronm ent . 3.2.1 general notes fi gure 3.2 handli ng cauti o ns 3.2.2 instal l a ti on (1) p lease use the driver of a low im pact when you use an electric driver. hdd is occasionally dam a ged by the im pact of the driver. (2 ) p lease o b serv e th e tig h t en in g to rq u e o f th e screw strictly. 6-32unc m a x. 0.59 nm (6 kgc m ) 3.2.3 r ecommended equipments content s m odel m aker wri s t st rap j x-1200-3056-8 s umitomo 3m esd esd mat 76000des (ask7876) comkyle shock l ow shock dri v er ss-3000 hios place the shock absorbing m a t on the operation table, and place esd mat on it. use th e w r ist strap . do not hit hdd each other. do not stack when carrying. do not place hdd vertically t o avoi d fal l i ng down. do not drop. shock absorbin g mat esd mat wrist strap
c141-e110-02en 3 - 4 3.3 mounti n g (1 ) d irectio n figure 3.3 illustrates norm a l direction for the disk drive. the disk drives can be m ounted in any di rect i on. hori z ont al m ount i ng wi t h t h e pcb faci ng down figure 3.3 d irection (2) f ram e the di sk encl osure (de) body i s connect ed t o si gnal ground (sg) and t h e m ounti ng fram e i s al so connected to signal ground. these are electrically shorted. note: use no.6-32unc screw for t h e m ount i ng screw and t h e screw l e ngt h shoul d sat i sfy t h e speci fi cat i on i n figure 3.5. (3) li m i t a t i on of si de-m ount i n g when t h e di sk dri v e i s m ount ed usi ng t h e screw hol es on bot h si de of t h e di sk dri v e, use t w o screw hol es shown i n fi gure 3.4. do not use t h e cent e r hol e. for screw l e ngt h, see fi gure 3.5.
c141-e110-02en 3 - 5 fi gure 3.4 l i m i t ati o n of si de-mounti ng figure 3.5 m ounting frame structure 5.0 or l e ss 4.5 or less 2 b fram e of system cabinet d etails o f b d etails o f a fram e of system cabinet screw screw pca de 2.5 2.5 2.5 a de side surface mount i ng bottom surface m ounting use these screw hol es do not use this screw hole
c141-e110-02en 3 - 6 (4 ) a m b ien t tem p eratu r e the t e m p erature condi t i ons for a di sk dri v e m ounted i n a cabi n et refer t o t h e am bi ent t e m p erature at a point 3 cm from the disk drive. pay attention to the air flow to prevent the de surface tem p erature from exceeding 60c. provide air circulation in the cabinet such that the pca side, in particular, receives sufficient cooling. to check the cooling efficiency, m easure the surface tem p eratures of the de. regardless of the am bient tem p erature, this surface tem p erature m u st m eet the standards listed in table 3.1. fi gure 3.6 shows t h e te m p erature m easurem ent poi nt . figure 3.6 surface temperature measurement points table 3.1 surface temperature measurement points and standard values no. m easurem ent poi nt tem p erature 1 de cover 60c max 1
c141-e110-02en 3 - 7 (5) s ervice area figure 3.7 shows how the drive m u st be accessed (service areas) during and after installation. figure 3.7 s ervice area (6) e xt ernal m a gnet i c fi el ds avoi d m ount i ng t h e di sk dri v e near st rong m a gnet i c sources such as l oud speakers. ensure t h a t the disk drive is not affected by external magnetic fields. [p side] - cabl e connect i o n - m ode set t i ng swi t c hes [r side] - m ount i ng screw hol e - m ount i ng screw hol e [q side] - m ount i ng screw hol e
c141-e110-02en 3 - 8 3.4 cabl e connecti o ns 3.4.1 d evice connector the di sk dri v e has t h e connect ors and t e rm i n al s l i st e d bel ow for connect i ng ext e rnal devi ces. fi gure 3.8 shows t h e lo cat i ons of t h ese connect ors and t e rm i n al s. power suppl y connect or (cn1) ata interface connector (cn1) fi gure 3.8 connector l o cations ata interface connect or m ode settin g pins power suppl y connect or (cn1)
c141-e110-02en 3 - 9 3.4.2 cabl e connector speci fi cati ons table 3.2 lists the recom m e nded specifications for the cable connectors for host system that do not support ul t ra dm a m odes great er t h an m ode 2. for host sy st em t h at support ul t r a dm a m odes great er t h an m ode 2, t h e 80-conduct o r cable assem b l i e s shal l be used. the 80-conduct o r cabl e assem b l i e s are m a nufact ured by amp or 3m . table 3.2 cable connector specifications nam e m odel m anufact urer cable socket (cl o sed-end t y p e) fcn-707b040-au/ b fujitsu cable socket (t hrough-end t y p e) fcn-707b040-au/ o fujitsu cabl e socket housing 1-480424-0 amp cont act 60617-4 amp note : the cable of twisted pairs and neighboring line separated individually is not allowed to use for the host interface cable. it is because that the location of signal lines in these cables is not fi xed, and so t h e probl em on t h e crosst al k am ong si gnal l i n es m a y occur. it is recom m e nded to use the ribbon cable for ata interface that cable length is less than 18 inch (46 cm ) and cable capacitance is less than 35 pico farad. also it is recom m e nded to use awg18 power suppl y cabl e . 3.4.3 d evice connection fi gure 3.9 shows how t o connect the devices. a t a i n t e r f a c e c a b l e p o w e r s uppl y c a b l e dc po w er supply disk dr i v e # 1 di sk dr i v e # 0 h o st sy st e m figure 3.9 cable connections power supply cabl e (cn1) ata interface cable (40-pi n, cn1)
c141-e110-02en 3 - 10 3.4.4 p ower supply connector (cn1) fi gure 3.10 shows t h e pi n assi gnm ent of t h e power suppl y connect or (cn1). (viewed from cable side) 4 3 2 1 + 5 vdc +5 v r etu r n + 12v r e t u r n + 12vdc 4 3 2 1 figure 3.10 power supply connector pins (cn1) 3.4.5 system confi g urati o n for ul tra dma host sy st em t h at support ul t r a dm a t r ansfer m odes great er t h an m ode 2 shal l not share i/ o port s. they shall provide separate drivers and separate receivers for each cable. a) the 80-conduct o r cable assem b l i e s shal l be used for sy st em s operat i ng at ul t r a dm a m odes greater than 2. the 80-coductor cable assem b lies m a y be used in place of 40-conductor cable assem b lies to im p r o v e sig n al q u ality fo r d ata tran sfer m o d es th at d o n o t req u i re an 8 0 - conduct o r cable assem b l y . and t h e 80-conduct o r cabl e assem b l y shal l m eet t h e fol l owi ng specifications. 1) the assem b ly utilizes a fine pitch cable to double the num ber of conductors available to the 40-pin connector. the grounds assigned by the interface are com m oned with the additional 40 conductors to provide a ground between each signal line and provide the effect of a comm on ground pl ane. 2) the cabl e assem b l y m a y cont ai n up t o 3 connect ors whi ch shall be uni quely col o red as fol l ows. al l connect ors shal l have posi t i on 20 bl ocked. the sy st em board connect or shal l have a bl ue base and bl ack ret a i n er. pi n 34 (pdiag-: cblid-) shall be connect ed t o ground and shal l not be wi red t o t h e cabl e assem b ly. connector device 0 shall have a black base and black retainer. connect or devi ce 1 shal l have a gray base and bl ack ret a i n er. pi n 28 (csel) shall not be connect ed t o t h e cabl e (cont act 28 m a y be rem oved t o m eet t h i s requirem e nt). th e cab le assem b ly m ay b e p r in ted w ith co n n ector id en tifiers. 3) ty pi cal cabl e charact eri st i c s are shown as fol l ows. cabl e: awg 30 (pi t c h: 0.635 m m ) si ngl e ended i m pedance: t y p i cal 80 w cable capacitance: typical 57 pf/m 4) the di m e nsi ons are shown i n fi gure 3.11.
c141-e110-02en 3 - 11 open c o n n ect o r 2 c o n n ect o r 1 sy st e m b o a r d c o n n ect o r p i n 2 (g r o un d) p i n 19 (g r o un d) p i n 22 (g r o un d) p i n 24 (g r o un d) p i n 26 (g r o un d) position 1 pin 34 contact (pdiag-:cblid- signal) 254. 0 t o 457. 2 m m (10 t o 18 i n c h ) 101. 6 t o 152. 4 m m (4 t o 6 i n c h ) 127. 0 t o 304. 8 m m (5 t o 12 i n c h ) symbolizes pin 34 conductor being cut p i n 30 (g r o un d) pin 34 p i n 40 (g r o un d) fi gure 3.11 cabl e confi g urati o n b) host sy st em t h at do support ul t r a dm a m odes great er t h an m ode 2 shal l ei t h er connect directly to the device without using a cable assem b ly, or determ ine the cable assem b ly type. determ ining the cable assem b ly type m a y be done either by the host sensing the condition of t h e pdiag-: cblid- si gnal (see fi gure 3.12), or by rel y i ng on i n form at i on from t h e devi ce (see fi gure 3.13). host s t h at rel y on i n form at i on from t h e devi ce shal l have a 0.047 m f capaci t o r connect ed from t h e pdiag-: cblid- si gnal t o ground. the t o l e rance on t h i s cap acito r sh all b e 2 0 % o r less.
c141-e110-02en 3 - 12 open h o s t d et ect ed c b li d - b el o w v il h o st de v i c e 0 d ev i ce 1 w i t h 80-c o n duc t o r c a b l e w i t h 40-c o n duc t o r c a b l e pdi ag- : c b l id- c o n duc t o r pdi ag- : c b l id- c o n duc t o r h os t d e t e c t e d c bl i d - a bove v ih host device 0 de v i ce 1 fi gure 3.12 cabl e type detecti on using cblid- signal (host sensing the condition of the cblid- signal) op e n 0. 047 m f 10% o r 20% h o st de v i c e 0 d ev i ce 1 w i t h 80-c o n duc t o r c a b l e w i t h 40-c o n duc t o r c a b l e p d ia g -: cb l id - c o n duc t o r p d ia g -: cb l id - c o n duc t o r i d en ti f y d ev i c e in f o r matio n w o r d 93 bi t 13: 1 d e vi c e d e t e c t e d c bl id - a bove v ih id enti f y d evic e in f o r matio n w o r d 93 bi t 13: 0 d ev i ce d et ect ed c b li d - b el o w v il host device 0 device 1 0. 047 m f 10% or 20% figure 3.13 cable type detection using identify device data (device sensing the condition of the cblid- signal)
c141-e110-02en 3 - 13 3.5 j umper settings 3.5.1 l ocati o n of setti ng jumpers fi gure 3.14 shows t h e l o cat i on of t h e jum pers t o select driv e confi gurat i on and funct i ons. figure 3.14 jumper location dc power connector interface connector 1 40 1 2
c141-e110-02en 3 - 14 3.5.2 f actory default setting figure 3.15 shows the default setting position at the factory. (master device setting) fi gure 3.15 factory defaul t setti ng 3.5.3 j umper configuration (1) d evice type master device (device #0) or slave device (device #1) is selected. 8 6 4 2 (a ) m a s t e r de v i c e = s h o r te d (b ) s l a v e de v i c e 9 7 5 3 1 8 6 4 2 9 7 5 3 1 fi gure 3.16 jumper setti ng of master or sl ave devi ce note: when t h e devi ce t y p e i s set by t h e jum per on t h e devi ce, t h e devi ce shoul d not be confi gured for cable selection. (2) c able select (csel) in cable select mode, the device can be configured either master device or slave device. for use of cable select function, unique interface cable is needed. dc power connector interface connector
c141-e110-02en 3 - 15 c s e l co n n ect ed t o t h e i n t er f a ce ca b l e s el ect i o n c a n b e d o n e b y th e s p e c ial in te r f ac e c a b l e . 8 6 4 2 9 7 5 3 1 fi gure 3.17 jumper setti ng of cabl e sel ect figures 3.18 and 3.19 show exam ples of cable selection using unique interface cables. by connect i ng t h e csel of t h e m a st er devi ce t o t h e csel li ne (conduct o r) of t h e cabl e and connect i ng i t t o ground furt her, t h e csel i s set t o l ow l e vel . the devi ce i s i d ent i f i e d as a m a st er device. at t h i s t i m e, t h e csel of t h e sl ave devi ce does not have a conduct o r. thus, si nce t h e sl ave devi ce i s not connect ed t o t h e csel conduct o r, t h e csel i s set t o hi gh l e vel . the devi ce i s identified as a slave device. open cs e l c onduct o r gnd s l a v e d ev i ce maste r d e v i c e h o st sy ste m figure 3.18 example (1) of cable sel ect s l a v e d e v i ce m a s ter device csel conductor gnd ho st sy st e m op e n fi gure 3.19 example (2) of cable select
c141-e110-02en 3 - 16 (3) speci al jum per set t i ngs (a) 2 .1 g b clip (lim it cap acity to 2 . 1 g b )/33.8 g b clip (lim it cap acity to 3 3 . 8 g b ) if t h e dri v e cannot be recogni zed by sy st em wi t h l e gacy bioss whi ch do not al l ow si ngl e vol um e si ze great er t h an approxi m a t e l y 2.1 gb, t h e fol l owi ng jum per set t i ngs shoul d be appl i e d. thi s jum per set t i ngs i s al so used as t h e 33.8 gb cl i p for m p g3409at. (m pg3409at does not have t h e 2.1 gb cl i p feat ure.) s l a v e d ev i ce m a s t er d ev i ce c a b l e select 8 6 4 2 9 7 5 3 1 8 6 4 2 9 7 5 3 1 8 6 4 2 9 7 5 3 1 m odel no. of cy l i nders no. of heads no. of sect ors c apaci t y MPG3102AT 4,092 16 63 2.1 gb mpg3153at 4,092 16 63 2.1 gb mpg3204at 4,092 16 63 2.1 gb mpg3307at 4,092 16 63 2.1 gb mpg3409at 16,383 16 63 33.8 gb (b) sl a ve present if the slave device does not use the device active/slave present (daspC) signal to indicate its presence, the device is configured as a master with slave present when the following jum per set t i ngs i s appl i e d. s l a v e p r es en t 8 6 4 2 9 7 5 3 1
c141-e110-02en 3 - 17 note: the fol l owi ng jum p er pl ug i s t h e recom m ended speci fi cat i on for jum per set t i ngs on t h i s device. part s nam e parts num ber m anufact urer rem a rks jum p er plug imas-9251h-gf iriso electronics co., ltd 2.54 m m pi t c h ? 0.64 m m 206-a-blk oupiin enterprise co., ltd
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c141-e110-02en 4 - 1 chapter 4 theor y of device opera t ion 4 . 1 outline 4.2 subassemblies 4.3 c i rcui t confi gurati on 4.4 pow er-on sequence 4.5 self-calibration 4.6 r ead/write circuit 4.7 s ervo control thi s chapt e r expl ai ns basi c desi gn concept s of t h e di sk dri v e. al so, t h i s chapt e r expl ai ns subassem b l i e s of the disk drive, each sequence, servo control, and electrical circuit blocks. 4 . 1 outline thi s chapt e r consi st s of t wo part s. fi rst part (sect i on 4.2) explai ns m echani cal assem b l i e s of t h e di sk dri v e. second part (sect i ons 4.3 t h rough 4.7) expl ai ns a servo i n form at i on recorded i n t h e di sk dri v e and dri v e cont rol m e t hod. 4.2 subassemblies the di sk dri v e consi st s of a di sk encl osure (de) and pri n t e d ci rcuit assem b l y (pca). the de cont ai ns al l m ovabl e part s i n t h e di sk dri v e, i n cl udi ng t h e di sk, spi ndl e, act uat o r, read /w rite h ead , an d air filter. fo r d e tails, see su b sectio n s 4 . 2 . 1 to 4 . 2 . 5 . the pca cont ai ns t h e cont rol circuit s for t h e di sk dri v e. the di sk dri v e has one pca. for det a i l s, see sect i ons 4.3. 4.2.1 disk the de cont ai ns t h e di sks wi t h an out er di am et er of 95 m m . the m pg3102at, m pg3153at, and m p g3204at have 1 di sk. the m p g3307at and m p g3409at have 2 di sks. the head contacts the disk each tim e the disk rotation stops; the life of the disk is 50,000 contacts or m o re. servo data is recorded on each cylinder (total 126). servo data written at factory is read out by the read/write head. for servo data, see section 4.7.
c141-e110-02en 4 - 2 4.2.2 h ead fi gure 4.1 shows t h e read/ w ri t e head st ructures. the num erals 0 t o 3 i ndi cat e read/ w ri t e heads. these heads are raised from the disk surface as the spindle m o tor approaches the rated rotation speed. figure 4.1 head structure spindle actuator m p g3102at 0 m p g3153at/mpg3204at spindle actuator 1 0 spindle actuator mpg3307at/ m p g3409at 3 2 1 0
c141-e110-02en 4 - 3 4.2.3 spindle the spindle consists of a disk stack assem b ly and spindle m o tor. the disk stack assem bly is act i v at ed by t h e di rect dri v e sensor-l ess dc spi ndl e m o t o r, whi ch has a speed of 5,400 rpm . the spi ndl e i s cont rol l e d wi t h det ect i ng a phase si gnal generat e d by count er el ect rom o t i v e vol t a ge of th e sp in d l e m o to r at startin g . a f ter th at, th e ro tatio n al sp eed is k ep t w ith d etectin g a servo inform ation. 4.2.4 a ctuator the actuator consists of a voice coil m o tor (vcm) and a head carriage. the vcm m oves the head carriage along the inner or outer edge of the disk. the head carriage position is controlled by feedi ng back t h e di fference of t h e t a rget posi t i on t h at i s det ect ed and reproduced from t h e servo inform ation read by the read/write head. 4 . 2 . 5 a ir filter th ere are tw o typ es o f air filters: a b r eather filter an d a circu l ation filter. the breather filter m a kes an air in and out of the de to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. w h en disk drives are transported under conditions w h ere th e air p r essure ch an g es a lo t, filtered air is circu l ated in th e d e. th e circu l ation filter clean s o u t d u st an d d i rt fro m in sid e th e d e. th e d i sk d r iv e cycles air continuously through the circulation filter through an enclosed loop air cycle system operated by a bl ower on t h e rot a t i ng di sk.
c141-e110-02en 4 - 4 4.3 c i rcui t confi gurati on fi gure 4.2 shows t h e di sk dri v e ci rcui t confi gurat i on. (1) r ead/write circuit th e read/w rite circu it co n sists o f tw o lsis; read /w rite p r eam p lifier (prea m p) an d read ch an n el (rdc). th e prea mp co n sists o f th e w r ite cu rrent sw itch circu it, th at flo w s th e w r ite cu rrent to th e h ead co il, an d th e v o ltage am p lifier circu it, th at am p litud es th e read o u t p u t fro m th e h ead . the rdc i s t h e read dem odulat i on ci rcuit usi ng t h e ext e nded part i a l response cl ass 4 (epr4), an d co n t ain s th e v iterb i d etecto r, p r o g r am m ab l e filter, ad ap tab l e tran sv ersal filter, tim es b ase generat o r, and dat a separat o r ci rcuit s. the rdc al so cont ai ns t h e 48/ 51 group coded recordi n g (gcr) encoder and decoder and servo dem odulat i on ci rcuit . (2) s ervo ci rcui t the posi t i on and speed of t h e voi ce coi l m o t o r are cont rol l e d by 2 cl osed-l oop servo usi ng t h e servo inform ation recorded on the data surface. the servo inform ation is an analog signal convert ed t o di gi t a l for processi ng by a m p u and t h en reconvert ed t o an anal og si gnal for cont rol of the voice coil m o tor. (3) s pi ndl e m o t o r dri v er ci rcui t the ci rcuit m easures t h e i n t e rval of a phase si gnal generat e d by count er-el ect rom o t i v e vol t a ge of a m o tor, or servo m a rk at the mpu and controls the m o tor speed com p aring target speed. (4) c ontroller circuit m a jor funct i ons are l i st e d bel ow. dat a buffer m a nagem e nt ata interface control and data transfer control sector format control defect m a nagem e nt ecc control error recovery and sel f-di a gnosi s
c141-e110-02en 4 - 5 hdc s h 7661 rd c cl - s h 3515 mcu a r m7t d mi cl- sh8671 him alay a 2.0 C p i o mo de - 4 C mul tiw o r d d ma mo de - 2 C u l tr a d m a mo de - 4 ( 66.6mb/s ) C u l tr a d m a mo de - 5 ( 100mb/s ) svc h a 13627 spm / v c m co ntr o l r/w bandw idth = 160.0 mb/s b u ffe r h e ad i c s r 1756 fl a s h r o m 64k 16 bits s e r ie s t e r m inatio n 40.0 mh z co ns o l e i /f ( r s 232c) s w itch i/ f at a da t a b u ffe r 256k 16 bits o p tio n ( 1024k 16 bits ) fi gure 4.2 m pg3xxxat b l o ck di agram 4.4 p ower-on sequence figure 4.3 describes the operation sequence of the disk drive at power-on. the outline is descri bed bel ow. a) aft e r t h e power i s t u rned on, t h e di sk dri v e execut e s t h e m pu bus t e st , i n t e rnal regi st er read/ w ri t e t e st , and work ram read/ w ri t e t e st . when t h e sel f-di a gnosi s t e rm i n at es su ccessfu lly, th e d i sk d r iv e starts th e sp in d l e m o to r. b) the di sk dri v e execut e s sel f-di a gnosi s (dat a buffer read/ w ri t e t e st ) aft e r enabl i ng response t o t h e ata bus. c) after confirm i ng that the spindle m o tor has reached rated speed, the disk drive releases the h ead s fro m th e actu ato r m ag n et lo ck m ech an ism b y ap p lying cu rrent to th e v c m. th is unlocks the heads which are parked at the inner circum ference of the disks. d) the di sk dri v e posi t i ons t h e heads ont o th e sa area and reads out t h e sy st em i n form at i on. e) the disk drive executes self-seek-calibration. this collects data for vcm torque and m echani cal ext e rnal forces appl i e d to t h e act uat o r, and updat e s th e cal i b rat i ng val u e. f) the drive becom e s ready. the host can issue com m a nds.
c141-e110-02en 4 - 6 c) b) a) r e le as e h e ad s f r o m ac tu ato r lo c k co n f ir min g s pin dle mo to r s peed se l f -di a gn o sis 2 ? d ata b uf f e r w r ite /r e ad te s t th e s pin dle mo to r s tar ts. se l f -di a gn o sis 1 ? mpu b us t e st ? i nne r re gi s t e r w r ite /r e a d te s t ? w o r k r a m w r ite /r e a d te s t s tar t po w e r o n d r iv e r e ad y s tate (c o mman d w aitin g s tate ) ex e c ute s e lf -c alibr ation in itial o n -tr ac k an d r e ad o ut o f s y s t e m in f o r matio n f) e) d) en d figure 4.3 p ow er-on operati on sequence
c141-e110-02en 4 - 7 4.5 self-calibration the disk drive occasionally perform s self-calibration in order to sense and calibrate m echanical external forces on the actuator, and vcm torque. this enables precise seek and read/write operat i ons. 4.5.1 self-calibration contents (1) sensing and com p ensating for external forces the actuator suffers from torque due to the fpc forces and winds accom p anying disk revolution. the t o rque vary wi t h t h e di sk dri v e and t h e cy l i nder where t h e head i s posi t i oned. to execut e stable fast seek operations, external forces are occasionally sensed. the firm ware of the drive m easures and stores the force (value of the actuator m o tor drive current ) t h at bal a nces t h e t o rque for st opping head st abl y . thi s i n cl udes t h e current offset i n t h e power am pl i f i e r ci rcuit and dac sy st em . the forces are com p ensated by adding the m easured value to the specified current value to the power am pl i f i e r. thi s m a kes t h e st abl e servo cont rol . to com p ensat e t o rque vary i ng by t h e cy l i nder, t h e di sk i s di vi ded i n t o 28 areas from t h e innerm ost to the outerm o st circum ference and the com p ensating value is m easured at the m easuring cylinder on each area at factory calibration. the m easured values are stored in the sa cy l i nder. in t h e sel f-cal i b rat i on, t h e com p ensat i ng val u e i s updat e d usi ng t h e val u e i n t h e sa cylin d er. (2) c om pensat i ng open l oop gai n torque constant value of the vcm has a dispersion for each drive, and varies depending on the cylinder that the head is positioned. to realize the high speed seek operation, the value that com p ensat e s t o rque const a nt val u e change and l oop gai n change of t h e whol e servo sy st em due t o tem p erature change is m easured and stored. for sensi ng, t h e fi rm ware m i xes t h e di st urbance si gnal t o t h e posi t i on si gnal at t h e st at e t h at t h e head is positioned to any cylinder. the firm ware calculates the loop gain from the position signal and stores the com p ensation value against to the target gain as ratio. for com p ensating, the direction current value to the power am plifier is m u ltiplied by the com p ensat i on val u e. by t h i s com p ensat i on, l oop gai n becom e s const a nt val u e and t h e st abl e servo cont rol i s real i zed. to com p ensate torque constant value change depending on cylinder, whole cylinders from m o st in n e r to m o st o u t er cylin d e r are d i v i d e d in to 1 5 p a rtitio n s at calib ratio n in th e facto r y, an d th e com p ensation data is m easured for representative cylinder of each partition. this m easured value is stored in the sa area. the com p ensation value at self-calibration is calculated using the value in the sa area.
c141-e110-02en 4 - 8 4.5.2 e xecution timing of self-calibration self-calib ratio n is ex ecu ted w h en : the power i s t u rned on. the self-calibration execution tim echart of the disk drive specifies self-calibration. the disk drive perform s self-calibration according to the tim echart based on the tim e elapsed from power-on. aft e r power-on, sel f-cal i b rat i on i s perform ed about every 30 m i nut es and when t h e host com m and i s not i ssued for 15 seconds. 4.5.3 command processi ng duri ng sel f-cal i brati on if the disk drive receives a com m a nd execution request from the host while executing self- calibration according to the tim echart, the disk drive term inates self-calibration and starts executing the com m a nd precedingly. in other words, if a disk read or write service is necessary, t h e di sk dri v e posi t i ons t h e head t o t h e t r ack request ed by t h e host , reads or wri t e s dat a . then restart s cal i b rat i on i f t h e host com m a nd i s not i ssued for 15 seconds. this enables the host to execute the com m a nd without waiting for a long tim e, even when the disk dri v e i s perform i ng sel f-cal i b rat i on. onl y t h e fi rst com m a nd execut i on wai t t i m e i s about m a xim um 100 m s.
c141-e110-02en 4 - 9 4.6 r ead/write circuit th e read /w rite circu it co n sists o f th e read /w rite p r eam p lifier (prea mp), th e w r ite circu it, th e read circu it, an d th e tim e b ase g en erato r in th e read ch an n el (rd c ). 4.6.1 r ead/write preamplifier (preamp) one pream p i s m ount ed on t h e fpc. the pream p consi st s of a 4-channel read pream pl i f i e r and a write current switch and senses a write error. each channel is connected to each data head. the head ic swi t c hes t h e heads by t h e seri al port (sden, sclk, sdata). the ic generat e s a wri t e error sense si gnal (wus) when a wri t e error occurs due t o head short - ci rcuit or head di sconnect i on. 4.6.2 write circuit the wri t e dat a i s out put from t h e hard di sk cont rol l e r (hdc) wi t h t h e nrz dat a form at , and sent to th e en co d e r circu it in th e rd c w ith syn c h r o n i zin g w ith th e w r ite clo c k . th e n rz w r ite d a ta is convert ed from 48-bi t s dat a t o 51-bi t s dat a by t h e encoder ci rcuit t h en sent t o t h e pream p, and th e d a ta is w r itten o n t o th e m e d i a. (1) 48/ 51 gcr the di sk dri v e convert s dat a usi ng t h e 48/ 51 group coded recordi ng (gcr) al gori t h m . (2 ) w rite pr eco m p en satio n w r ite precom p ensation com p ensates, during a write process, for write non-linearity generated at reading. 4.6.3 r ead circuit the head read signal from the preamp is regulated by the autom a tic gain control (agc) circuit. then the output is converted into the sam p led read data pulse by the program m a ble filter circuit and t h e fir adapt a t i on equal i zer ci rcuit . thi s cl ock si gnal i s convert ed i n t o t h e nrz dat a by t h e 48/ 51 gcr decoder ci rcuit based on t h e read dat a m a xi m u m - l i k el i hood-det ect ed by t h e vi t e rbi d etectio n circu it, th en is sen t to th e h d c . (1) agc circuit th e a g c circu it au to m a tically reg u l ates th e o u t p u t am p litu d e to a co n stan t v a lu e ev en w h e n th e input am plitude level fluctuates. the agc am plifier output is m a intained at a constant level even when t h e head out put fluct u at es due t o t h e head charact eri st i c s or out er/ i nner head posi t i ons.
c141-e110-02en 4 - 10 (2 ) p ro g r am m a b l e filter the program m a ble filter circuit has a low-pass filter function that elim inates unnecessary high frequency noi se com ponent and a hi gh frequency boost -up funct i on t h at equal i zes t h e waveform of the read signal. cut-off frequency of the low-pass filter and boost-up gain are controlled from each dac circuit in read channel. the mpu optim izes the cut-off frequency and boost-up gain according to the transfer frequency of each zone. (3) f ir (digital finite im pulse response equalization filter) adaptation circuit the fir provi des support for changi ng equal i zat i on needs from head t o head and zone t o zone. th e fir is a sp ecialized d i g ital filter w ith ten in d ep en d en tly co n t ro lled co efficien ts. (4 ) v iterb i d etectio n circu i t the viterbi detection circuit dem odulates data according to the survivor path sequence. (5) d ata separator circuit the dat a separat o r ci rcuit generat e s cl ocks i n sy nchroni zat i on wi t h t h e out put of t h e adapt i v e equal i zer ci rcuit . to wri t e dat a , t h e vfo ci rcuit generat e s cl ocks i n sy nchroni zat i on wi t h t h e cl ock si gnals from a sy nt hesizer. (6) 48/ 51 gcr decoder thi s circuit convert s th e 51-bi t s read dat a i n t o t h e 48-bi t s nrz dat a . 4.6.4 t ime base generator circuit th e d r iv e u ses co n stan t d en sity reco rd in g to in crease to tal cap acity. th is is d i fferen t fro m th e convent i onal m e t hod of recordi ng dat a wi t h a fi xed dat a t r ansfer rat e at al l dat a area. in t h e constant density recording m e thod, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant. the dri v e di vi des dat a area i n t o 15 zones t o set t h e dat a t r ansfer rat e . tabl e 4.1 descri bes t h e dat a transfer rate and recording density (bpi) of each zone.
c141-e110-02en 4 - 11 table 4.1 t ransfer rate of each z o ne th e mpu tran sfers th e d ata tran sfer rate setu p d ata to th e rd c th at in clu d es th e tim e b ase g en erato r circu it to ch an g e th e d ata tran sfer rate. mpg3153at/3307at MPG3102AT/3204at/ 3409at zone cy l i nder t ransfer rat e [mb/s] zone cy l i nder transfer rat e [mb/s] 0 0 t o 2655 38.59 0 0 to 3231 49.80 1 2656 t o 5311 38.59 1 3232 t o 5727 48.47 2 5312 t o 6527 38.04 2 5728 t o 9055 46.47 3 6528 t o 9151 36.71 3 9056 t o 11071 45.10 4 9152 t o 11839 35.29 4 11072 t o 13055 43.76 5 11840 t o 13823 34.12 5 13056 t o 15743 41.76 6 13824 t o 15743 32.94 6 15744 t o 17663 40.47 7 15744 t o 18751 30.98 7 17664 t o 20031 38.59 8 18752 t o 19583 30.59 8 20032 t o 22335 36.71 9 19584 t o 21887 29.02 9 22336 t o 23999 35.29 10 21888 t o 24191 27.45 10 24000 t o 25375 34.12 11 24192 t o 25631 26.35 11 25376 t o 27135 32.55 12 25632 t o 27039 25.29 12 27136 t o 28799 30.98 13 27040 t o 28895 23.53 13 28800 t o 30431 29.41 14 28896 t o 25927 22.75 14 30432 t o 30783 27.45
c141-e110-02en 4 - 12 4.7 s ervo control th e actu ato r m o to r an d th e sp in d l e m o to r are su b m itted to serv o co n t ro l. th e actuato r m o to r is cont rol l e d for m ovi ng and posi t i oni ng t h e head t o t h e t rack cont ai ni ng t h e desi red dat a . to t u rn the disk at a constant velocity, the actuator m o tor is controlled according to the servo data that is w r itten o n th e d ata side b efo reh an d . 4.7.1 s ervo control circuit fi gure 4.4 i s t h e bl ock di agram of t h e servo cont rol ci rcuit . the fol l owi ng descri bes t h e funct i ons of t h e bl ocks: (5) (1) (2) ( 3) (4) p. am p . csr: cur r e nt se nse re sisto r vc m: voice c o il motor sp indl e mo t o r con t rol dsp unit ser v o bu rs t captu re svc mp u csr driv er da c ad c p o sitio n sense head vcm curren t vcm sp indle mot o r (7) (6) figure 4.4 b lock diagram of servo control circuit (1) microprocessor unit (mpu) the mpu in clu d es d sp u n it, etc., an d th e mpu starts th e sp in d l e m o to r, m o v es th e h ead s to th e reference cylinders, seeks the specified cylinder, and executes calibration according to the internal operat i ons of t h e m p u. the m a jor i n t e rnal operat i ons are l i st e d bel ow. a. spindle m o tor start starts the spindle m o tor and accelerates it to norm a l speed when power is applied.
c141-e110-02en 4 - 13 b. m ove head t o reference cy l i nder d r iv es th e v cm to p o sitio n th e h ead at th e an y cylin d e r in th e d a ta area. th e lo g i cal in itial cylinder is at the outerm o st circum ference (cylinder 0). c. seek to specified cylinder d r iv es th e v c m to p o sition th e h ead to th e sp ecified cylind er. d . calib ratio n senses and stores the therm a l offset between heads and the m echanical forces on the actuator, and st ores t h e cal i b rat i on val u e.
c141-e110-02en 4 - 14 fi gure 4.5 p hysi cal sector servo confi g urati o n on di sk surface (2) servo burst capture circuit the four servo si gnals can be sy nchronousl y det ect ed by t h e strob si gnal, ful l - wave rect i f i e d in teg r ated . (3) a / d convert er (adc) the a/d converter (adc) receives the servo signals are integrated, converts them to digital, and transfers th e d i g ital sig n al to th e d sp u n it. ogb data area igb expand servo frame (126 servo frames per revolution) cy1 n + 1 cy1 n cy1 n C 1 (n: odd number) diameter direction circumference d irectio n erase: dc erase area w / r recovery servo mark gray code w / r recovery servo mark gray code w/r recovery servo mark gray code erase servo a erase servo a erase servo b erase servo b erase servo b servo c erase servo c erase erase servo d erase servo d pad
c141-e110-02en 4 - 15 (4) d / a convert er (dac) the d/ a convert er (dac) convert s t h e vcm dri v e current val u e (di g i t a l val u e) cal cul a t e d by t h e dsp uni t i n t o anal og val u es and t r ansfers t h em t o t h e power ampl i f i e r. (5 ) p o w e r am p lifier the power am pl i f i e r feeds current s, correspondi ng t o t h e dac out put signal vol t a ge t o t h e vcm . (6) s pi ndl e m o t o r cont rol ci rcui t th e sp in d l e m o to r co n t ro l circu it co n t ro ls th e sen so r-less sp in d l e m o to r. th is circu it d etects n u m b er o f rev o l u tio n o f th e m o to r b y th e in terru p t g en erated p eriod i cally, co m p ares w ith th e target revolution speed, then flows the current into the m o tor coil according to the differentiation (aberration). (7) d river circuit the driver circuit is a power am plitude circuit that receives signals from the spindle m o tor control circuit and feeds currents to the spindle m o tor. (8) v cm current sense resistor (csr) thi s resist or control s current at t h e power am pl i f i e r by convert i ng t h e vcm current i n t o vol t a ge and feedi ng back. 4.7.2 data-surface servo format fi gure 4.5 descri bes t h e phy si cal l a y out of t h e servo fram e . the t h ree areas i ndi cat ed by (1) t o (3) i n figure 4.5 are descri bed bel ow. (1) inner guard band the head is in contact with the disk in this space when the spindle starts turning or stops, and the rot a t i onal speed of t h e spi ndl e can be cont rol l e d on t h i s cy l i nder area for head m ovi ng. (2) d ata area this area is used as the user data area and sa area. (3) out er guard band this area is located at outer position of the user data area, and the rotational speed of the spindle can be cont rol l e d on t h i s cy l i nder area for head m ovi ng.
c141-e110-02en 4 - 16 4.7.3 servo frame format as t h e servo i n form at i on, t h e dri v e uses t h e t wo-phase servo generat e d from t h e gray code and pos a t o d. thi s servo i n form at i on i s used for posi t i oni ng operat i on of radi us di rect i on and posit i on det ect i on of ci rcum st ance di recti on. the servo fram e consi st s of 6 bl ocks; wri t e / r ead recovery , servo m a rk, pream bl e, gray code, pos a t o d and pad. fi gure 4.6 shows t h e servo fram e form at . fi gure 4.6 126 servo frames i n each track 0.72 m s 1.81 m s asm ssm scd posa posb posc posd pad r/w recover y field 6.63 m s data data data 88.18 m s servo fra m e servo fra m e 0.16 m s 0.17 m s 0.53 m s 0.74 m s 0.56 m s 0.56 m s 0.56 m s 0.80 m s pa
c141-e110-02en 4 - 17 (1) w rite/read recovery this area is used to absorb the write/read transient and to stabilize the agc. (2) servo m a rk (asm, ssm) this area generates a tim ing for dem odulating the gray code and position-dem odulating pos a to d by det ect i ng t h e servo m a rk. (3) pream ble this area is used to synchronize with the pll, which is used to search the ssm by detecting the asm . (4) g ray code (i ncl udi ng i ndex bi t ) (scd) thi s area i s used as cy l i nder address. the dat a i n t h i s area i s convert ed i n t o t h e bi nary dat a by t h e gray code dem odulat i on ci rcuit . (5) pos a, pos b, pos c, pos d this area is used as position signals between tracks, and the device control at on-track so that pos a lev el eq u als to po s b lev el. (6) p ad thi s area i s used as a gap bet w een servo and dat a . 4.7.4 a ctuator motor control the voi ce coi l m o t o r (vcm ) i s cont rol l e d by feedi ng back t h e servo dat a recorded on t h e dat a surface. the mpu fetches the position sense data on the servo fram e at a constant interval of sam p l i ng t i m e, execut e s cal cul a t i on, and updat e s th e vcm dri v e current . the servo control of t h e act uat o r i n cl udes t h e operat i on t o m ove t h e head t o t h e reference cylin d er, th e seek o p eratio n to m o v e th e h ead to th e targ et cylin d er to read o r w r ite d ata, an d th e t rack-fol l owi ng operat i on t o posi t i on t h e head ont o t h e t a rget t rack. (1) operation to m ove the head to the reference cylinder the m pu m oves t h e head t o t h e reference cy l i nder when t h e power i s t u rned. the reference cylin d er is in th e d ata area. when power i s appl i e d t h e heads are m oved from t h e i nner ci rcum ference shunt zone t o t h e norm a l servo dat a zone i n t h e fol l owi ng sequence: a) micro current is fed to the vcm to press the head against the inner circum ference.
c141-e110-02en 4 - 18 b) a current i s fed t o t h e vcm t o m ove t h e head t oward t h e out er ci rcum ference. c) w h en the servo m a rk is detected the head is m oved slowly toward the outer circum ference at a constant speed. d) if the head is stopped at the reference cylinder from there. track following control starts. (2) seek operation upon a data read/write request from the host, the mpu confirm s the necessity of access to the disk. if a read or instruction is issued, the mpu seeks the desired track. the m pu feeds t h e vcm current vi a t h e d/ a convert er and power am pl i f i e r t o m ove t h e head. the mpu calculates the difference (speed error) between the specified target position and the current position for each sam p ling tim ing during head m oving. the mpu then feeds the vcm drive current by setting the calculated result into the d/a converter. the calculation is digitally executed by the firm ware. w h en the head arrives at the target cylinder, the track is followed. (3) track fol l owi ng operat i o n except duri ng head m ovem e nt t o t h e reference cy l i nder and seek operat i on under t h e spi ndl e ro tates in stead y sp eed , th e mpu d o es track fo llo w i n g co n t ro l. to p o sition th e h ead at th e cen ter of a track, the dsp drives the vcm by feeding m i cro current. for each sam p ling tim e, the vcm d r iv e cu rrent is d eterm in ed b y filterin g th e p o sition d i fferen ce b etw een th e targ et p o sition an d th e p o sition clarified b y th e d etected p o sition sen se d ata. th e filterin g in clu d es serv o co m p en satio n . th ese are d i g itally co n t ro lled b y th e firm w are. 4.7.5 spindle motor control h all-less th ree-p h ase eig h t -p o l e m o to r is u sed fo r th e sp in d l e m o to r, an d th e 3 - p h ase fu ll/half- wave anal og current cont rol ci rcuit i s used as t h e spi ndl e m o t o r dri v er (call e d svc hereaft e r). the fi rm ware operat e s on t h e m p u m a nufact ured by fuji t su. the spi ndl e m o t o r i s cont rol l e d by sendi ng several si gnals from t h e m pu t o t h e svc. there are t h ree m odes for t h e spi ndl e control ; start m ode, acceleration m ode, and stable rotation m ode. (1) start m ode when power i s suppl i e d, t h e spi ndl e m o t o r i s st art e d i n t h e fol l owi ng sequence: a) aft e r t h e power i s t u rned on, t h e m pu sends a si gnal t o t h e svc t o charge t h e change pum p capaci t o r of t h e svc. the charged am ount defi nes t h e current t h at flows i n t h e spi ndl e m o t o r. b) when t h e charge pum p capaci t o r i s charged enough, t h e m pu set s t h e svc t o t h e m o t o r st art m ode. then, a current (approx. 1.6 a) fl ows i n t o t h e spi ndl e m o t o r. c) the svc generat e s a phase swi t c hi ng si gnal by i t sel f, and changes t h e phase of t h e current fl owed i n t h e m o t o r i n t h e order of (v-phase t o u-phase), (w-phase t o u-phase), (w-phase t o v-phase), (u-phase t o v-phase), (u-phase t o w-phase), and (v-phase t o w-phase) (aft er t h at , repeat i ng t h i s order).
c141-e110-02en 4 - 19 d) duri ng phase swi t c hi ng, t h e spi ndl e m o t o r st art s rot a t i ng i n l ow speed, and generat e s a count er el ect rom o t i v e force. the svc det ect s t h i s count er el ect rom o t i v e force and report s t o t h e mpu usi ng a phase si gnal for speed det ect i on. e) the m pu i s wai t i ng for a phase si gnal. when no phase si gnal i s sent for a speci fi c period, t h e m pu reset s t h e svc and st art s from t h e begi nni ng. when a phase si gnal i s sent , t h e svc enters the acceleration m ode. (2) a cceleration m ode in th is m o d e, th e mpu sto p s to sen d th e p h ase sw itchi n g sig n al to th e sv c. th e sv c starts a phase swi t c hi ng by i t sel f based on t h e count er el ect rom o t i v e force. then, rot a t i on of t h e spi ndl e m o tor accelerates. the mpu calculates a rotational speed of the spindle m o tor based on the phase signal from the svc, and accelerates till the rotational speed reaches 5,400 rpm . w h en the rotational speed reaches 5,400 rpm , the svc enters the stable rotation m ode. (3) s t a bl e rot a t i on m ode the m pu cal cul a t e s a t i m e for one revol ut i on of t h e spi ndl e m o t o r based on t h e phase si gnal from the svc. the mpu takes a difference between the current tim e and a tim e for one revol ut i on at 5,400 rpm t h at t h e m pu al ready recogni zed. then, t h e m pu keeps t h e rot a t i onal speed t o 5,400 rpm by chargi ng or di schargi ng t h e charge pum p for t h e di fferent t i m e. for exam pl e, when t h e act ual rot a t i onal speed i s 5,600 rpm , t h e t i m e for one revol ut i on i s 10.714 m s . and, t h e t i m e for one revol ut i on at 5,400 rpm i s 11.111 m s. therefore, t h e m p u di scharges t h e charge pum p for 0.397 m s k (k: const a nt val u e). thi s m a kes t h e fl owed current i n t o t h e m o t o r l ower and t h e rot a t i onal speed down. when t h e act ual rot a t i onal speed i s l a t e r t h an 5,400 rpm , t h e m p u charges t h e pum p t h e ot her way . thi s cont rol (chargi ng/ di schargi ng) i s perform ed every 1/ 4 revol ut i on.
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c141-e110-02en 5 - 1 chapter 5 interf ace 5.1 physical interface 5.2 l ogi cal interface 5.3 host commands 5.4 command protocol 5.5 u l t ra dma feature set 5 . 6 timing
c141-e110-02en 5 - 2 5.1 physical interface 5.1.1 interface si gnals table 5.1 shows the interface signals. table 5.1 interface signals description host dir dev acrorym cable select see note c sel chip select 0 ? cs0C chip select 1 ? cs1C data bus bit 0 ? dd0 data bus bit 1 ? dd1 data bus bit 2 ? dd2 data bus bit 3 ? dd3 data bus bit 4 ? dd4 data bus bit 5 ? dd5 data bus bit 6 ? dd6 data bus bit 7 ? dd7 data bus bit 8 ? dd8 data bus bit 9 ? dd9 data bus bit 10 ? dd10 data bus bit 11 ? dd11 data bus bit 12 ? dd12 data bus bit 13 ? dd13 data bus bit 14 ? dd14 data bus bit 15 ? dd15 device active or slave present s ee note daspC device address bit 0 ? da0 device address bit 1 ? da1 device address bit 2 ? da2 dma acknowledge ? dmackC dma request ? dmarq in terru p t request ? intrq i/o read ? diorC dma ready during ultra dma data in bursts ? hdmardyC data strobe during ultra dma data out bursts ? hstrobe i/o ready ? iordy dma ready during ultra dma data out bursts ? ddmardyC data strobe during ultra dma data in bursts ? dstrobe i/o write ? diowC stop during ultra dma data bursts ? stop passed diagnostics see note pdiagC cable type detection cblidC reset ? resetC note see signal descriptions
c141-e110-02en 5 - 3 5.1.2 si g nal assi gnment on the connector table 5.2 shows the signal assignm ent on the interface connector. table 5.2 s ignal assignment on the interface connector pi n no. si gnal p i n no. si gnal 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 resetC data7 data6 data5 data4 data3 data2 data1 data0 gnd dm arq diowC, stop diorC, hdm ardyC, hstrobe iordy, ddm ardyC, dstrobe dm ackC intrq da1 da0 cs0C daspC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 gnd data8 data9 data10 data11 data12 data13 data14 data15 (key) gnd gnd gnd csel gnd reserved pdiagC, cblidC da2 cs1C gnd [si gnal ] [i/ o] [descri p t i on] resetC i r eset sig n al fro m th e h o s t. th is sig n al is lo w activ e an d is asserted for a mini m u m of 25 m s duri ng power on. the devi ce has a 10 k w pul l - up resi st or on t h i s si gnal . data 0-15 i/ o s i x t een-bi t bi-di r ect i onal dat a bus bet w een t h e host and t h e devi ce. these signals are used for data transfer diowC, stop i d iowC i s t h e st robe si gnal assert ed by t h e host t o wri t e devi ce regist ers or t h e dat a port . d i o w C sh all b e n e g a ted b y th e h o st p r io r to in itiatio n o f an u ltra dm a burst . stop shal l be negat e d by t h e host before dat a i s t r ansferred i n an ul t r a dm a burst . assert i on of stop by t h e host duri ng an ul t r a dm a burst si gnal s t h e t e rm i n at i on of t h e ul t r a dm a burst .
c141-e110-02en 5 - 4 [si gnal ] [i/ o] [descri p t i on] diorC i diorC i s t h e st robe si gnal assert ed by t h e host t o read devi ce regist ers or t h e dat a port . hdm ardyC i hdm ardyC i s a fl ow cont rol si gnal for ul t ra dm a dat a i n burst s. th is sig n al is asserted b y th e h o st to in d i cate to th e d ev i ce th at th e host is ready to receive ultra dma data in bursts. the host m a y negat e hdm ardy- t o pause an ul t r a dm a dat a i n burst . hstrobe i hstrobe i s t h e dat a out strobe si gnal from t h e host for an ul t r a dm a dat a out burst . bot h t h e ri si ng and fal l i ng edge of hstrobe l a t c h t h e dat a from data 0-15 i n t o t h e devi ce. the host m a y st op generat i ng hstrobe edges t o pause an ul t r a dm a dat a out burst . in trq o in terru p t sig n al to th e h o st. thi s signal i s negat e d in t h e fol l owi ng cases: C assert i on of resetC si gnal C reset by srst of t h e devi ce cont rol regi st er C wri t e t o t h e com m and regi st er by t h e host C read of t h e st at us regi st er by t h e host C com p l e t i on of sect or dat a t r ansfer (wi t hout readi ng t h e st at us regi st er) when t h e devi ce i s not sel ect ed or i n t e rrupt i s disabled, t h e intrq si gnal shal l be i n a hi gh i m pedance st at e. cs0C i c hi p sel ect signal decoded from t h e host address bus. thi s signal i s used by t h e host t o sel ect t h e com m a nd bl ock regi st ers. cs1C i c hi p sel ect signal decoded from t h e host address bus. thi s signal i s used by t h e host t o sel ect t h e cont rol block regi st ers. da 0-2 i binary decoded address signals asserted by the host to access task file registers. key C key pi n for prevent i on of erroneous connect or i n sert i o n pidagC i/ o thi s si gnal i s an i nput m ode for t h e m a st er devi ce and an out put m ode for t h e sl ave devi ce i n a dai sy chai n confi gurat i on. thi s signal i ndi cat es th at t h e slave devi ce has been com p l e t e d sel f di agnost i c s. thi s si gnal i s pul l e d up t o +5 v t h rough 10 k w resistor at each device. cblidC i / o thi s signal i s used t o det ect t h e cabl e t y p e (80 or 40-conduct o r cab le) in stalled in th e system . th is sig n al is p u lled u p to +5 v t hrough 10 k w resistor at each device. d a spC i/o th i s is a tim e-m u ltiplex ed sig n al th at in d i cates th at th e d ev i ce is active and a slave device is present. thi s si gnal i s pul l e d up t o +5 v t h rough 10 k w resistor at each device.
c141-e110-02en 5 - 5 [si gnal ] [i/ o] [descri p t i on] i o r d y o th is sig n al is n eg ated to ex ten d th e h o s t tran sfer cycle o f an y h o s t register access (read or w r ite) when the device is not ready to respond to a d a ta tran sfer req u e st. d d m a r d y C o ddm ardyC i s a fl ow cont rol si gnal for ul t ra dm a dat a out burst s. th is sig n al is asserted b y th e d ev i ce to in d i cate to th e h o s t th at th e device is ready to receive ultra dma data out bursts. the device m a y negat e ddm ardyC t o pause an ul t ra dm a dat a out burst . dstrobe o dstrobe i s t h e dat a i n strobe si gnal from t h e devi ce for an ul t r a dm a dat a i n burst . bot h t h e ri si ng and fal l i ng edge of dstrobe l a t c h th e dat a from data 0-15 i n t o t h e host . the devi ce m a y stop generat i ng dstrobe edges t o pause an ul t r a dm a dat a i n burst . csel i this signal to configure the device as a m a ster or a slave device. when csel si gnal i s grounded, t h e idd i s a m a st er devi ce. when csel si gnal i s open, t h e idd i s a sl ave devi ce. thi s signal i s pul l e d up wi t h 10 k w resistor. dm ackC i the host sy st em assert s t h i s si gnal as a response t h at t h e host sy st em receive data or to indicate that data is valid. dm arq o thi s signal i s used for dm a tr ansfer bet w een t h e host syst em and t h e devi ce. the devi ce assert s th i s signal when t h e devi ce com p l e t e s t h e preparat i on of dm a dat a t r ansfer t o t h e host syst em (at readi ng) or from t h e host syst em (at wri t i ng). the di rect i on of dat a t ransfer i s cont rol l e d by t h e ior- and iow- si gnals. in ot her word, t h e devi ce negat e s th e dm arq si gnal aft e r t h e host syst em assert s th e dm ackC si gnal. when t h ere i s anot her dat a t o be t r ansferred, t h e devi ce assert s th e dm arq si gnal agai n. when t h e dm a dat a t ransfer i s perform ed, iocw16C, cs0C and cs1- si gnals are not assert ed. the dm a dat a t r ansfer i s a 16-bi t dat a t r ansfer. the devi ce has a 10 k w pul l -down resi st or on t h i s si gnal. gnd C g rounded note: "i" i ndi cat es i nput signal from t h e host t o t h e devi ce. "o" i ndi cat es out put signal from t h e devi ce t o t h e host . "i/ o " indi cat es com m on out put or bi -di r ect i onal signal bet w een t h e host and t h e devi ce.
c141-e110-02en 5 - 6 5.2 logi cal interface the device can operate for com m a nd execution in either address-specified m ode; cylinder-head- sector (chs) or logi cal bl ock address (lba) m ode. the identify device i n form at i o n i ndi cat es whet h er t h e devi ce support s t h e lba m ode. when t h e host sy st em speci fi es t h e lba m ode by set t i ng bi t 6 i n t h e devi ce/ head regi st er t o 1, hs3 t o hs0 bi t s of t h e device/ head register indicates the head no. under the lba m ode, and all bits of the cylinder high, cylinder low, and sect or num ber regi st ers are lba bi t s. the sector no. under the lba m ode proceeds in the ascending order with the start point of lba0 (defined as follows). lba0 = [cy l i nder 0, head 0, sect or 1] even i f t h e host sy st em changes t h e assi gnm ent of t h e chs m ode by t h e initialize device parameter com m and, the sector lba address is not changed. lba = [((cylinder no.) (num ber of head) + (head no.)) (num ber of sect or/ t r ack)] + (sector no.) C 1 5.2.1 i/o registers com m uni cat i on bet w een t h e host sy st em and t h e devi ce i s done t h rough i nput -out put (i/ o) regist ers of t h e devi ce. these i/ o regist ers can be sel ect ed by t h e coded si gnals, cs0C, cs1C, and da0 t o da2 from t h e host syst em . tabl e 5.3 shows t h e codi ng address and t h e funct i on of i/ o regi st ers.
c141-e110-02en 5 - 7 table 5.3 i/o registers i/o registers read operation write operation command block registers 1 0 0 0 0 dat a dat a x' 1f0' 1 0 0 0 1 error regi st er feat ures x' 1f1' 1 0 0 1 0 sect or count sect or count x' 1f2' 1 0 0 1 1 sect or num ber s ect or num ber x'1f3' 1 0 1 0 0 cylin d er lo w c ylin d er lo w x '1 f4 ' 1 0 1 0 1 cy l i nder hi gh cy l inder high x'1f5' 1 0 1 1 0 devi ce/ head devi ce/ head x'1f6' 1 0 1 1 1 st at us com m and x'1f7' 1 1 x x x (inval i d ) (inval i d) cont rol block registers 0 1 1 1 0 al t e rnat e st at us devi ce cont rol x ' 3 f6' 0 1 1 1 1 x' 3f7' notes: 1. the data register for read or write operation can be accessed by 16 bit data bus (data0 t o data15). 2. the registers for read or write operation other than the data registers can be accessed by 8 bi t dat a bus (data0 t o data7). 3. when readi ng t h e dri v e address regi st er, bi t 7 i s hi gh-i m pedance st at e. 4. the lba m ode i s speci fi ed, t h e devi ce/ head, cy l i nder hi gh, cy l i nder low, and sect or num ber regi sters indicate lba bits 27 to 24, 23 to 16, 15 to 8, and 7 to 0. host i/ o address da0 da1 da2 cs1C cs0C
c141-e110-02en 5 - 8 5.2.2 command block registers (1) d ata register (x' 1 f0' ) the dat a regi st er i s a 16-bi t regi st er for dat a bl ock t r ansfer bet w een t h e device and t h e host system . (2) e rror register (x' 1 f1' ) the error register indicates the status of the com m and executed by the device. the contents of t h i s regi st er are val i d when t h e err bi t of t h e st at us regi st er i s 1. thi s regi st er cont ai ns a di agnost i c code aft e r power i s t u rned on, a reset , or t h e executive device diagnostic com m a nd i s execut e d. [st a t u s at t h e com p l e t i on of com m a nd execut i on ot her t h an di agnost i c com m a nd] bit 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 i c r c u n c x idnf x abrt tk0nf amnf x: unused - bit 7: interface crc error (icrc). this bit indicates that an interface crc error has occurred duri ng an ul t ra dm a dat a t ransfer. the cont ent of t h i s bi t i s not appl i cabl e for m u l t i word dm a t ransfers. - bit 6: uncorrectable data error (unc). this bit indicates that an uncorrectable data error has been encount ered. - bi t 5: unused - bi t 4: id not found (idnf). thi s bi t i ndi cat es an error except for, uncorrect abl e error and sb not found, and abort e d com m a nd. - bi t 3: unused - bi t 2: abort e d com m a nd (abrt). thi s bit i ndi cat es t h at t h e request ed com m a nd was abort e d due t o a devi ce st at us error (e.g. not ready , wri t e faul t ) or t h e com m a nd code was i nvali d . - bi t 1: track 0 not found (tk0nf). thi s bi t i ndi cat es t h at t rack 0 was not found duri n g recalibrate com m a nd execution. - bi t 0: address m a rk not found. thi s bit i ndi cat es t h at an sb not found error has been encount ered.
c141-e110-02en 5 - 9 [di a gnost i c code] x' 01' : no error det ect ed. x' 02' : hdc regi st er com p are error x' 03' : d ata buffer com p are error. x' 05' : r om sum check error. x' 80' : d evi ce 1 (sl a ve devi ce) fai l e d. error regi st er of t h e m a st er devi ce i s val i d under t wo devi ces (m ast e r and sl ave) confi gurat i on. if t h e sl ave devi ce fai l s, th e m a st er devi ce post s x80 or (t he di agnost i c code) wi t h i t s own st at us (x' 01' t o x' 05' ). however, when t h e host sy st em sel ect s th e sl ave devi ce, t h e di agnost i c code of t h e sl ave device i s post e d. (3) features register (x' 1 f1' ) the features register provides specific feature to a com m and. for instance, it is used with set features com m a nd to enable or disable caching. (4) sector count regi st er (x'1 f2' ) the sector count regist er i ndi cat es t h e num ber of sectors of dat a t o be t r ansferred i n a read or wri t e operat i on bet w een t h e host sy st em and t h e devi ce. when t h e val u e i n t h i s regi st er i s x' 00' , t h e sect or count i s 256. w h en this register indicates x'00' at the com p letion of the com m and execution, this indicates that the com m and is com p leted successfully. if the com m and is not com p leted successfully, this regist er i ndi cat es t h e num ber of sect ors t o be t r ansferred t o com p l e t e t h e request from t h e host sy st em . that i s, t h i s regi st er i ndi cat es t h e num ber of rem a i n i ng sectors t h at t h e dat a has not been transferred due to the error. the cont ent s of t h i s regi st er has ot her defi ni t i on for t h e fol l owi ng com m ands; initialize device parameters, format track, set features, idle, standby and set multiple mode. (5) sector num ber register (x' 1 f3' ) the cont ent s of t h i s regi st er i ndi cat es t h e st art i ng sector num ber for t h e subsequent com m a nd. the sect or num ber shoul d be bet w een x' 01' and [t he num ber of sect ors per t rack defi ned by initialize device parameters com m a nd. under t h e lba m ode, t h i s regi st er i ndi cat es lba bi t s 7 t o 0.
c141-e110-02en 5 - 10 (6) c ylinder low register (x' 1 f4' ) the cont ent s of t h i s regi st er i ndi cat es l ow-order 8 bi t s of t h e st art i ng cy l i nder address for any disk-access. at the end of a com m a nd, the contents of this register are updated to the current cylinder num ber. under t h e lba m ode, t h i s regi st er i ndi cat es lba bi t s 15 t o 8. (7) c y l i nder hi gh regi st er (x' 1 f5' ) the contents of this register indicates high-order 8 bits of the disk-access start cylinder address. at the end of a com m a nd, the contents of this register are updated to the current cylinder num ber. the hi gh-order 8 bi t s of t h e cy l i nder address are set t o t h e cy l i nder hi gh regi st er. under t h e lba m ode, t h i s regi st er i ndi cat es lba bi t s 23 t o 16. (8) d evice/head register (x'1f6') the contents of this register indicate the device and the head num ber. w h en executing initialize device parameters com m and, the contents of this register defines "t he num ber of heads m i nus 1". bit 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 x l x d ev hs3 h s2 hs1 hs0 - bi t 7: unused - bi t 6: l. 0 for chs m ode and 1 for lba m ode. - bi t 5: unused - bi t 4: dev bi t . 0 for t h e m a st er devi ce and 1 for t h e sl ave devi ce. - bi t 3: hs3 chs m ode head address 3 (2 3 ). lba bi t 27. - bi t 2: hs2 chs m ode head address 3 (2 2 ). lba bi t 26. - bi t 1: hs1 chs m ode head address 3 (2 1 ). lba bi t 25. - bit 0: hs0 chs mode head address 3 (2 0 ). lba bit 24.
c141-e110-02en 5 - 11 (9) status register (x' 1 f7' ) the contents of this register indicate the status of the device. the contents of this register are updated at the com p letion of each com m a nd. w h en the bsy bit is cleared, other bits in this regi st er shoul d be val i d at ed wi t h i n 400 ns. when t h e bsy bi t i s 1, ot her bi t s of t h i s regi st er are in v alid. w h en th e h o st system read s th is reg i ster w h ile an in terru p t is p en d i n g , it is co n sid ered to be t h e int e rrupt acknowl edge (t he host sy st em acknowl edges t h e i n t e rrupt ). any pendi ng i n t e rrupt i s cleared (negat i ng intrq si gnal) whenever t h i s regi st er i s read. bit 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 bsy drdy df dsc drq 0 0 err - bit 7: busy (bsy) bit. this bit is set whenever the com m a nd register is accessed. then t h i s bi t i s cl eared when t h e com m a nd i s com p l e t e d. however, even i f a com m and i s b ein g ex ecu ted , th is b it is 0 w h ile d a ta tran sfer is b ein g req u ested (d rq b it = 1).when bsy bi t i s 1, t h e host sy st em shoul d not wri t e t h e com m a nd bl ock regist ers. if t h e host sy st em reads any com m and bl ock regi st er when bsy bi t i s 1, t h e content s of t h e st at us regi st er are post e d. thi s bi t i s set by t h e devi ce under fol l owi ng condi t i ons: (a) w i t h i n 400 ns aft e r reset- i s negat e d or srst i s set i n t h e device control reg i ster, th e bsy b it is set. th e bsy b it is cleared , w h en th e reset p r o cess is co m p leted . the bsy bit is set for no longer than 15 seconds after the idd accepts reset. (b) w ithin 400 ns from the host system starts writing to the com m a nd register. (c) w ith in 5 m s fol l owi ng t ransfer of 512 by t e s dat a duri ng execut i on of t h e read sector(s), write sector(s), format track, or write buffer com m a nd. w ith in 5 m s fol l owi ng t ransfer of 512 by t e s of dat a and t h e appropri a t e number of ecc by t e s duri ng execut i on of read long or write long com m and. - bi t 6: device ready (drdy) bi t . thi s bi t i ndi cat es t h at t h e devi ce i s capabl e t o respond to a com m a nd. the idd checks its status when it receives a com m a nd. if an error is detected (not ready st at e), t h e idd cl ears t h i s bi t t o 0. thi s i s cl eared t o 0 at power-on and i t i s cleared until the rotational speed of the spindle m o tor reaches the steady speed. - bit 5 : th e d ev i ce w r ite fau lt (d f) b it. th is b it in d i cates th at a d ev i ce fau lt (w rite fau lt) condi t i on has been det ect ed. if a w r ite fau lt is d e tected d u r in g co m m a n d ex ecu tio n , th is b it is latch e d an d retain ed until the device accepts the next com m a nd or reset. - bit 4: device seek com p lete (dsc) bit. this bit indicates that the device heads are posit i oned over a t r ack. in th e id d , th is b it is alw ays set to 1 after th e sp in -u p co n t ro l is co m p leted .
c141-e110-02en 5 - 12 - bit 3 : d ata req u est (d rq ) b it. th is b it in d i cates th at th e d ev i ce is read y to tran sfer d ata of word uni t or by t e uni t bet w een t h e host syst em and t h e devi ce. - bi t 2: al way s 0. - bi t 1: al way s 0. - bit 0 : error (err) b it. th is b it in d i cates th at an error w as d etected w h ile th e p r ev io u s com m a nd was bei ng execut e d. the error regi st er i ndi cat es t h e addi t i onal inform ation of the cause for the error. (10) com m a nd regi st er (x' 1 f7' ) the com m a nd regi st er cont ai ns a com m a nd code bei ng sent t o t h e devi ce. aft e r t h i s regist er i s w r itten , th e co m m a n d ex ecu tio n starts im m e d i ately. table 5.3 lists the executable com m ands and their com m a nd codes. this table also lists the necessary param e ters for each com m a nd which are written to certain registers before the co m m an d reg i ster is w r itten .
c141-e110-02en 5 - 13 5.2.3 control bl ock regi s ters (1) a lternate status register (x' 3 f6' ) the alternate status register contains the sam e inform ation as the status register of the com m and bl ock regi st er. the onl y di fference from t h e st at us regi st er i s t h at a read of t h i s regi st er does not i m pl y int e rrupt acknowl edge and intrq si gnal i s not reset . bit 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 bsy d rdy df dsc drq 0 0 err (2) d evice control register (x' 3 f6' ) the devi ce cont rol regi st er cont ai ns devi ce i n t e rrupt and soft ware reset . bit 7 b it 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxx s rstnien0 - bit 2 : srst is th e h o s t so ftw are reset b it. w h en th is b it is set, th e d ev i ce is h eld reset state. w h en two device are daisy chained on the interface, setting this bit resets both device sim u l t a neousl y . the sl ave devi ce i s not requi red t o execut e t h e dasp- handshake. - bit 1 : n i en b it en ab les an in terru p t (in trq sig n al) fro m th e d ev i ce to th e h o st. w h en th is bi t i s 0 and t h e devi ce i s sel ect ed, an i n t e rrupt i on (intrq si gnal) can be enabl e d t h rough a t ri -st at e buffer. when t h i s bi t i s 1 or t h e devi ce i s not sel ect ed, t h e intrq si gnal i s i n t h e hi gh-im pedance st at e. 5.3 host commands the host sy st em i ssues a com m a nd t o t h e devi ce by wri t i ng necessary param e t e rs i n rel a t e d regist ers i n t h e com m a nd bl ock and wri t i ng a com m and code i n t h e com m a nd regi st er. the device can accept the com m a nd when the bsy bit is 0 (the device is not in the busy status). the host sy st em can hal t t h e uncom pl et ed com m a nd execut i on onl y at execut i on of hardware or software reset. when t h e bsy bi t i s 1 or t h e drq bi t i s 1 (t he devi ce i s request i ng t h e dat a t r ansfer) and t h e host sy st em wri t e s to t h e com m a nd regi st er, t h e correct devi ce operat i on i s not guarant eed.
c141-e110-02en 5 - 14 5.3.1 command code and parameters table 5.4 l i st s t h e support e d com m a nds, com m a nd code and t h e regi st ers t h at needed param e t e rs are w r itten . table 5.4 command code and parameters (1 of 2) com m and code (bit) param e ters used 76543210 f r s c s n c y d h r e a d s e c t o r ( s ) 0 010000 r n y y y y r e a d m u l t i p l e 1 100010 0 n y y y y r e a d d m a 1 100100 r n y y y y r e a d v e r i f y s e c t o r ( s ) 0 100000 r n y y y y w r i t e m u l t i p l e 1 100010 1 n y y y y w r i t e d m a 1 100101 r n y y y y w r i t e v e r i f y 0 011110 0 n y y y y w r i t e s e c t o r ( s ) 0 011000 r n y y y y r e c a l i b r a t e 0 0 0 1 xxx xnnnn d s e e k 0 1 1 1 xxx xnn y y y initialize device diagnostic 1 001000 1 n y n n y i d e n t i f y d e v i c e 1 110110 0 nnnn d i d e n t i f y d e v i c e d m a 1 110111 0 nnnn d s e t f e a t u r e s 1 110111 1 y n * nnd s e t m u l t i p l e m o d e 1 100011 0 nynn d execute device diagnostic 1 001000 0 n n n n d * f o r m a t t r a c k 0 101000 0 n n y * y y r e a d l o n g 0 010001 r n y y y y w r i t e l o n g 0 011001 r n y y y y r e a d b u f f e r 1 110010 0 n n n n d w r i t e b u f f e r 1 110100 0 n n n n d idle 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 1 ny n n d idle im m e diate 1 1 0 1 0 1 1 0 0 0 1 0 0 0 1 1 nn n n d standby 1 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 ny n n d com m a nd nam e
c141-e110-02en 5 - 15 table 5.4 command code and parameters (2 of 2) com m and code (bit) param e ters used 7 654321 0 f r s csncydh standby im m e diate 1 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 nn n n d sleep 1 1 0 1 0 1 1 0 1 0 0 1 0 1 1 0 nn n n d check power m ode 1 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 nn n n d s m a r t 1 011000 0 y y y y d f l u s h c a c h e 1 110011 1 n n n n d s e c u r i t y d i s a b l e p a s s w o r d 1 111011 0 nnnn d s e c u r i t y e r a s e p r e p a r e 1 111001 1 nnnn d s e c u r i t y e r a s e u n i t 1 111010 0 nnnn d security freeze lock 1 111010 1 nnnn d s e c u r i t y s e t p a s s w o r d 1 111000 1 nnnn d s e c u r i t y u n l o c k 1 111001 0 nnnn d set m ax address 1 111100 1 nyyy y read native m ax address 1 111100 0 nnnn d notes: fr : features register cy: cylinder registers sc : sect or count regi st er dh : dri v e/ head regi st er sn : sect or num ber regi st er r: r = 0 or 1 y: necessary to set param e ters y*: necessary t o set param e t e rs under t h e lba m ode. n: necessary t o set param e t e rs (the param e t e r i s i gnored i f i t i s set . ) n * : may set p aram eters d: the devi ce param e t e r i s val i d , and t h e head param e t e r i s i gnored. d*: the com m a nd i s addressed t o t h e m a st er devi ce, but bot h t h e m a st er device and t h e sl ave device execute it. x: do not care com m a nd nam e
c141-e110-02en 5 - 16 5.3.2 command descriptions the contents of the i/o registers to be necessary for issuing a com m a nd and the exam ple i ndi cat i on of t h e i/ o regi st ers at com m a nd com p l e t i on are shown as fol l owi ng i n t h i s subsect i on. exam pl e: read sector(s) at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) b it 76543210 1f7 h (cm) 00100000 1f6 h (dh) l dv head no. / lba [msb] 1f5 h (ch) start cylinder address [msb] / lba 1f4 h (cl) start cylinder address [lsb] / lba 1f3 h (sn) start sector no. / lba [lsb] 1f2 h (sc) transfer sector count 1f1 h (fr) xx at command completion (i/o registers contents to be read) b it 76543210 1f7 h (st) error information 1f6 h (dh) l dv end head no. / lba [msb] 1f5 h (ch) end cylinder address [msb] / lba 1f4 h (cl) end cylinder address [lsb] / lba 1f3 h (sn) end sector no. / lba [lsb] 1f2 h (sc) x00 1f1 h (er) error information cm: com m and register fr: features register dh: devi ce/ head regi st er st: st at us regi st er ch: cylinder high register er: error register cl: cy l i nder low regi st er l: lba (l ogi cal bl ock address) set t i ng bi t sn: sector number register dv: device address. bit sc: sector count register x, xx: do not care (no necessary to set)
c141-e110-02en 5 - 17 notes: 1 . w h en th e l b it is sp ecified to 1 , th e lo w er 4 b its o f th e d h reg i ster and all b its o f th e ch , cl and sn registers indicate the lba bits (bits of the dh register are the msb (m ost significant bit) and bits of the sn register are the lsb (least significant bit). 2 . at error occurrence, t h e sc regi st er i ndi cat es t h e rem a i n i ng sect or count of dat a t r ansfer. 3 . in th e tab l e in d i catin g i/o reg i sters co n t en ts in th is su b s ectio n , b it in d i catio n is o m itted . (1) r ead sector(s) (x' 20' or x' 21' ) thi s com m a nd reads dat a of sect ors speci fi ed i n t h e sect or count regi st er from t h e address speci fi ed in t h e devi ce/ head, cy l i nder hi gh, cy l i nder low and sect or num ber regi st ers. num ber of sect ors can be speci fi ed t o 256 sect ors i n m a xi m u m . to speci fy 256 sect ors readi ng, ' 00' i s speci fi ed. for t h e drq, intrq, and bsy prot ocol s rel a t e d t o dat a t ransfer, see subsect i on 5.4.1. if the head is not on the track specified by the host, the device perform s a im plied seek. after the head reaches to the specified track, the device reads the target sector. th e d r q b it o f th e statu s reg i ster is alw ays set p r io r to th e d ata tran sfer reg ard less o f an error condi t i on. upon the com p letion of the com m a nd execution, com m a nd block registers contain the cylinder, head, and sect or addresses (i n t h e chs m ode) or l ogi cal bl ock address (i n t h e lba m ode) of t h e last sector read. if an error occurs in a sector, the read operation is term inated at the sector where the error occurred. com m a nd bl ock regi st ers cont ai n t h e cy l i nder, t h e head, and t h e sect or addresses of t h e sector (i n t h e chs m ode) or t h e l ogi cal bl ock address (i n t h e lba m ode) where t h e error occurred, and rem a i n i ng num ber of sect ors of whi ch dat a was not t ransferred. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) 0010000r 1f6 h (dh) l dv start head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) st art cy l i nder no. [m sb] / lba st art cylinder no. [lsb] / lba start sector no. / lba [lsb] transfer sector count xx r = 0 or 1
c141-e110-02en 5 - 18 at com m and com p l e t i on (i/ o regi st ers cont ent s t o be read) 1f7 h (st) status information 1f6 h (dh) l dv end head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) end cy l i nder no. [m sb] / lba end cy l i nder no. [lsb] / lba end sect or no. / lba [lsb] 00 (*1) error information *1 if t h e com m a nd i s t e rm i n at ed due t o an error, t h e rem a i n i ng num ber of sect ors of whi ch dat a was not t r ansferred i s set i n t h i s regi st er. (2) r ead multiple (x' c 4' ) thi s com m a nd operat e s si m i l a rl y t o t h e read sector(s) com m a nd. the devi ce does not generate an interrupt (assertion of the intrq signal) on each every sector. an interrupt is generat e d aft e r t h e t r ansfer of a bl ock of sect ors for whi ch t h e num ber i s speci fi ed by t h e set multiple mode com m a nd. th e im p l em en tatio n o f th e rea d mu ltiple co m m a n d is id en tical to th at o f th e rea d sector(s) com m a nd except that the num ber of sectors is specified by the set multiple m ode com m a nd are t ransferred wi t hout i n t e rveni ng i n t e rrupt s. in t h e read m u ltiple com m a nd operat i on, t h e drq bi t of t h e st at us regi st er i s set onl y at th e st art of t h e dat a bl ock, and is not set on each sector. the num ber of sect ors (bl o ck count ) t o be t r ansferred wi t hout i n t e rrupt i on i s speci fi ed by t h e set m u ltiple m ode com m a nd. the set m u ltiple m ode com m and shoul d be execut e d pri o r to th e rea d mu ltiple co m m an d . when t h e read m u ltiple com m a nd i s i ssued, t h e sect or count regi st er cont ai ns t h e num ber of sect ors request ed (not a num ber of t h e bl ock count or a num ber of sect ors i n a bl ock). upon receipt of this com m a nd, the device executes this com m a nd even if the value of the sector count regi st er i s l e ss t h an t h e defi ned bl ock count (t he val u e of t h e sect or count shoul d not be 0). if t h e num ber of request ed sect ors i s not di vi ded evenl y (havi ng t h e sam e num ber of sectors [bl o ck count ] ), as m a ny ful l bl ocks as possi bl e are t r ansferred, t h en a fi nal parti a l bl ock i s t r ansferred. the num ber of sectors i n t h e parti a l bl ock t o be t r ansferred i s n where n = rem a i nder of ("num ber of sect ors"/ " bl ock count "). if the read multiple com m a nd is issued before the set multiple mode com m and is execut e d or when t h e read m u ltiple com m and i s di sabled, t h e devi ce reject s t h e read m u ltiple com m a nd wi t h an aborted com m and error. if an error occurs, readi ng sect or i s st opped at t h e sect or where t h e error occurred. com m and bl ock regi st ers cont ai n t h e cy l i nder, t h e head, t h e sect or addresses (i n t h e chs m ode) or t h e l ogi cal bl ock address (i n t h e lba m ode) of t h e sect or where t h e error occurred, and rem a i n i n g num ber of sect ors t h at had not t r ansferred aft e r th e sect or where t h e error occurred. an interrupt is generated when the drq bit is set at the beginning of each block or a partial block.
c141-e110-02en 5 - 19 fi gure 5.1 shows an exam pl e of t h e execut i on of t h e read m u ltiple com m a nd. bl ock count speci fi ed by set m u ltiple m ode com m a nd = 4 (num ber of sect ors i n a bl ock) read multiple com m a nd specifies; num ber of request ed sect ors = 9 (sect or count regi st er = 9) num ber of sect ors i n i n com p l e t e bl ock = rem a i nder of 9/ 4 =1 s tatu s r e ad s tatu s r e ad s tatu s r e ad co mman d i s s ue bs y in t r q dr dy ~ p ar ame te r w r ite 9 5 6 7 8 1 2 3 4 p ar tial bl oc k bl oc k bl oc k s ect o r tr an s f e r r e d dr q figure 5.1 e xecuti on exampl e of read multiple command at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) 11000100 1f6 h (dh) l d v start head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) st art cy l i nder no. [m sb] / lba st art cy l i nder no. [lsb] / lba st art sect or no. / lba [lsb] transfer sect or count xx at com m and com p l e tion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) l d v end head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) end cy l i nder no. [m sb] / lba end cy l i nder no. [lsb] / lba end sect or no. / lba [lsb] 00 h (*1) error inform ation *1 if t h e com m and is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register.
c141-e110-02en 5 - 20 (3) r ead dm a (x' c 8' or x' c9' ) thi s com m a nd operat e s si m i l a rl y t o t h e read sector(s) com m a nd except for fol l owi ng events. the dat a t r ansfer st art s at t h e ti m i ng of dm arq si gnal assert i on. the devi ce cont rol s t h e assert i on or negat i on t i m i ng of t h e dm arq si gnal. the device posts a status as the result of com m and execution only once at com p letion of the d a ta tran sfer. when an error, such as an unrecoverabl e m e di um error, t h at t h e com m a nd execut i on cannot be cont i nued i s det ect ed, t h e dat a t r ansfer i s st opped wi t hout t r ansferri ng dat a of sect ors aft e r t h e erred sect or. the devi ce generat e s an i n t e rrupt usi ng t h e intrq si gnal and post s a st at us t o t h e host sy st em . the form at of the error inform ation is the sam e as the read sector(s) com m a nd. in lba m ode the l ogi cal bl ock address i s speci fi ed usi ng t h e st art head no., st art cy l i nder no., and fi rst sector no. fi el ds. at com m a nd com p l e t i on, t h e l ogi cal bl ock address of t h e l a st sect or and rem a i n i n g num ber of sect ors of whi ch dat a was not t r ansferred, l i k e in t h e chs m ode, are set . the host syst em can sel ect t h e dm a tr ansfer m ode by usi ng t h e set features com m and. 1) m u l t i word dm a t ransfer m ode 2: set s t h e fr regi st er = x' 03' and sc regi st er = x' 22' by t h e set features com m a nd 2) ul t ra dm a t ransfer m ode 2: set s t h e fr regi st er = x' 03' and sc regi st er = x' 42' by t h e set features com m a nd at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) 1100100r 1f6 h (dh) l dv start head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) st art cy l i nder no. [m sb] / lba st art cy l i nder no. [lsb] / lba start sector no. / lba [lsb] transfer sector count xx r = 0 or 1
c141-e110-02en 5 - 21 at com m and com p l e t i on (i/ o regi st ers cont ent s t o be read) 1f7 h (st) status information 1f6 h (dh) l dv end head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) end cy l i nder no. [m sb] / lba end cy l i nder no. [lsb] / lba end sect or no. / lba [lsb] 00 (*1) error information *1 if t h e com m a nd i s t e rm i n at ed due t o an error, t h e rem a i n i ng num ber of sect ors of whi ch dat a was not t r ansferred i s set i n t h i s regi st er. (4) r ead verify sector(s) (x' 40' or x' 41' ) th is co m m an d o p erates sim ilarly to th e rea d secto r (s) co m m an d ex cep t th at th e d ata is n o t tran sferred to th e h o s t system . after all requested sectors are verified, the device clears the bsy bit of the status register and generat e s an i n t e rrupt . upon t h e com p l e t i on of t h e com m a nd execut i on, t h e com m and bl ock regist ers cont ai n th e cy l i nder, head, and sect or num ber of t h e la st sect or veri fi ed. if an error occurs, the verify operation is term inated at the sector where the error occurred. the com m a nd bl ock regi st ers cont ai n t h e cy l i nder, t h e head, and t h e sector addresses (i n t h e chs m ode) or t h e l ogi cal bl ock address (i n t h e lba m ode) of t h e sect or where t h e error occurred. the sector count regi st er i ndi cat es t h e num ber of sect ors t h at have not been veri fi ed. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) 0100000r 1f6 h (dh) l dv start head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) st art cy l i nder no. [m sb] / lba start cylinder no. [lsb] / lba start sector no. / lba [lsb] transfer sector count xx r = 0 or 1
c141-e110-02en 5 - 22 at com m and com p l e t i on (i/ o regi st ers cont ent s t o be read) 1f7 h (st) status information 1f6 h (dh) l dv end head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) end cy l i nder no. [m sb] / lba end cy l i nder no. [lsb] / lba end sect or no. / lba [lsb] 00 (*1) error information *1 if t h e com m a nd i s t e rm i n at ed due t o an error, t h e rem a i n i ng num ber of sect ors of whi ch dat a was not t r ansferred i s set i n t h i s regi st er. (5) w rite sector(s) (x' 30' or x' 31' ) this com m and writes data of sectors from the address specified in the device/head, cylinder hi gh, cy l i nder low, and sect or num ber regi st ers t o t h e address speci fi ed i n t h e sect or count regi st er. num ber of sect ors can be speci fi ed t o 256 sect ors i n m a xi m u m . dat a t r ansfer begi ns at t h e sect or speci fi ed i n t h e sect or num ber regi st er. for t h e drq, intrq, and bsy protocols rel a t e d to dat a t r ansfer, see subsect i on 5.4.2. if the head is not on the track specified by the host, the device perform s a im plied seek. after the head reaches to the specified track, the device writes the target sector. th e d ata sto r ed in th e b u ffer, an d crc co d e an d ecc b ytes are w r itten to th e d ata field o f th e correspondi ng sect or(s). upon t h e com p l e t i on of t h e com m a nd execut i on, t h e com m a nd bl ock reg i sters co n t ain th e cylind er, h ead , an d secto r ad d r esses of th e last secto r w r itten . if an error o ccu rs d u r in g m u ltiple secto r w r ite o p eratio n , th e w r ite o p eratio n is term in ated at th e sector where t h e error occurred. com m a nd bl ock regi st ers cont ai n t h e cy l i nder, t h e head, t h e sector addresses (i n t h e chs m ode) or t h e l ogi cal bl ock address (i n t h e lba m ode) of t h e sector where the error occurred. then the host can read the com m and block registers to determ ine what error has occurred and on which sect or t h e error has occurred. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h ( cm) 0011000r 1f6 h (dh) l dv start head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) st art cy l i nder no. [m sb] / lba st art cy l i nder no. [lsb] / lba st art sector no. / lba [lsb] transfer sector count xx r = 0 or 1
c141-e110-02en 5 - 23 at com m and com p l e t i on (i/ o regi st ers cont ent s t o be read) 1f7 h (st) status information 1f6 h (dh) l dv end head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) end cy l i nder no. [m sb] / lba end cy l i nder no. [lsb] / lba end sect or no. / lba [lsb] 00 (*1) error information *1 if t h e com m a nd i s t e rm i n at ed due t o an error, t h e rem a i n i ng num ber of sect ors of whi ch dat a was not t r ansferred i s set i n t h i s regi st er. (6) w rite multiple (x' c 5' ) thi s com m and i s si m i l a r t o t h e write sector(s) com m a nd. the devi ce does not generat e interrupts (assertion of the intrq signal) on each sector but on the transfer of a block which cont ai ns t h e num ber of sect ors for whi ch t h e num ber i s defi ned by t h e set m u ltiple m ode c o mma n d . th e im p l em en tatio n o f th e w r ite mu ltiple co m m an d is id en tical to th at o f th e w r ite sector(s) com m a nd except that the num ber of sectors is specified by the set multiple m ode com m a nd are t ransferred wi t hout i n t e rveni ng i n t e rrupt s. in t h e write m u ltiple com m a nd operat i on, t h e drq bi t of t h e st at us regi st er i s requi red t o set onl y at t h e st art of t h e data block, not on each sector. the num ber of sect ors (bl o ck count ) t o be t r ansferred wi t hout i n t e rrupt i on i s speci fi ed by t h e set m u ltiple m ode com m a nd. the set m u ltiple m ode com m and shoul d be execut e d pri o r to the w r ite multiple com m a nd. when t h e write m u ltiple com m a nd i s i ssued, t h e sect or count regi st er cont ai ns t h e num ber of sect ors request ed (not a num ber of t h e bl ock count or a num ber of sect ors i n a bl ock). upon receipt of this com m a nd, the device executes this com m a nd even if the value of the sector count regi st er i s l e ss t h an t h e defi ned bl ock count t h e val u e of t h e sect or count shoul d not be 0). if t h e num ber of request ed sect ors i s not di vi ded evenl y (havi ng t h e sam e num ber of sectors [bl o ck count ] ), as m a ny ful l bl ocks as possi bl e are t r ansferred, t h en a fi nal parti a l bl ock i s t r ansferred. the num ber of sect ors i n t h e part i a l bl ock t o be t r ansferred i s n where n = rem a i nder of ("num ber of sect ors"/ " bl ock count "). if the w r ite multiple com m a nd is issued before the set multiple mode com m a nd is execut e d or when write m u ltiple com m and i s di sabled, t h e devi ce reject s t h e write m u ltiple com m a nd wi t h an aborted com m and error. di sk errors encount ered duri ng execut i on of t h e write m u ltiple com m a nd are post e d aft e r at t e m p t i ng t o wri t e t h e bl ock or t h e part i a l bl ock t h at was t r ansferred. wri t e operat i on ends at t h e sect or where t h e error was encount ered even i f t h e sect or i s i n t h e m i ddl e of a bl ock. if an error occurs, t h e subsequent bl ock shal l not be t r ansferred. int e rrupt s are generat e d when t h e drq bi t of t h e status register is set at the beginning of each block or partial block.
c141-e110-02en 5 - 24 the cont ent s of t h e com m a nd bl ock regi st ers rel a t e d t o addresses aft e r t h e t r ansfer of a dat a bl ock contai ni ng an erred sect or are undefi ned. to obt ai n a val i d error i n form at i on, t h e host shoul d ret r y dat a t r ansfer as an i ndi vi dual request s. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h ( c m ) 110 00101 1f6 h (dh) l dv start head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) st art cy l i nder no. [m sb] / lba st art cy l i nder no. [lsb] / lba st art sect or no. / lba [lsb] transfer sector count xx at com m and completion (i/o registers contents to be read) 1f7 h (st) status inform ation 1f6 h (dh) l dv end head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) end cy l i nder no. [m sb] / lba end cy l i nder no. [lsb] / lba end sect or no. / lba [lsb] 00 h error information note: w h en th e co m m an d term in ates d u e to erro r, o n ly th e d v b it an d th e erro r in fo rm atio n field are valid. (7) w rite dm a (x'ca' or x' cb' ) th is co m m an d o p erates sim ilarly to th e w r ite secto r (s) co m m an d ex cep t fo r fo llo w i n g events. the dat a t r ansfer st art s at t h e ti m i ng of dm arq si gnal assert i on. the devi ce cont rol s t h e assert i on or negat i on t i m i ng of t h e dm arq si gnal. the device posts a status as the result of com m and execution only once at com p letion of the d a ta tran sfer. when an error, such as an unrecoverabl e m e di um error, t h at t h e com m a nd execut i on cannot be conti nued i s det ect ed, t h e dat a t r ansfer i s st opped wi t hout t r ansferri ng dat a of sect ors aft e r t h e erred sect or. the devi ce generat e s an i n t e rrupt usi ng t h e intrq si gnal and post s a st at us t o t h e host system . the form at of the error inform ation is the sam e as the w r ite sector(s) c o mma n d . a host sy st em can be sel ect t h e fol l owi ng tr ansfer m ode usi ng th e set features com m a nd.
c141-e110-02en 5 - 25 1) m u l t i word dm a t ransfer m ode 2: set s t h e fr regi st er = x' 03' and sc regi st er = x' 22' by t h e set features com m a nd 2) ul t ra dm a t ransfer m ode 2: set s t h e fr regi st er = x' 03' and sc regi st er = x' 42' by t h e set features com m a nd at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h ( cm) 1100101r 1f6 h (dh) l dv start head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) st art cy l i nder no. [m sb] / lba st art cy l i nder no. [lsb] / lba st art sect or no. / lba [lsb] transfer sector count xx r = 0 or 1 at com m and completion (i/o registers contents to be read) 1f7 h (st) status inform ation 1f6 h (dh) l dv end head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) end cy l i nder no. [m sb] / lba end cy l i nder no. [lsb] / lba end sect or no. / lba [lsb] 00 (*1) error information *1 if t h e com m a nd i s t e rm i n at ed due t o an error, t h e rem a i n i ng num ber of sect ors of whi ch dat a was not t r ansferred i s set i n t h i s regi st er. (8) w rite verify (x'3c') th is co m m an d o p erates sim ilarly to th e w r ite secto r (s) co m m an d ex cep t th at th e d ev i ce v erifies each sector im m e diately after being written. the verify operation is a read and check for data errors without data t ransfer. any error t h at i s det ect ed duri ng t h e veri fy operat i on i s post e d. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) 00111100 1f6 h (dh) l dv start head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) st art cy l i nder no. [m sb] / lba st art cylinder no. [lsb] / lba start sector no. / lba [lsb] transfer sector count xx
c141-e110-02en 5 - 26 at com m and com p l e t i on (i/ o regi st ers cont ent s t o be read) 1f7 h (st) status information 1f6 h (dh) l dv end head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) end cy l i nder no. [m sb] / lba end cy l i nder no. [lsb] / lba end sect or no. / lba [lsb] 00 (*1) error information *1 if t h e com m a nd i s t e rm i n at ed due t o an error, t h e rem a i n i ng num ber of sect ors of whi ch dat a was not t r ansferred i s set i n t h i s regi st er. (9) r ecalibrate (x' 1x' , x: x' 0' t o x' f' ) this com m a nd perform s the rezero. upon receipt of this com m a nd, the device sets bsy bit of the status register and perform s a rezero. w h en the device com p letes the rezero, the device updates t h e st at us regi st er, cl ears t h e bsy bi t , and generat e s an i n t e rrupt . thi s com m a nd can be i ssued i n t h e lba m ode. at command issuance (i/o registers setting contents) 1f7 h (cm) 0001xxxx 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at command completion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information
c141-e110-02en 5 - 27 (10) seek (x' 7x' , x : x' 0' t o x' f' ) this com m and perform s a seek operation to the track and selects the head specified in the com m a nd bl ock regist ers. aft e r com p l e t i ng t h e seek operat i on, t h e devi ce cl ears t h e bsy bi t i n t h e st at us regi st er and generat e s an i n t e rrupt . the idd al way s set s t h e dsc bi t (dri ve seek com p l e t e stat us) of t h e st at us regi st er t o 1. in t h e lba m ode, t h i s com m a nd perform s t h e seek operat i on t o t h e cy l i nder and head posi t i on i n which the sector is specified with the logical block address. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h ( c m ) 0111xxxx 1f6 h (dh) l dv head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) cy l i nder no. [m sb] / lba cylinder no. [lsb] / lba sector no. / lba [lsb] xx xx at com m and com p letion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) l dv head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) cy l i nder no. [m sb] / lba cy l i nder no. [lsb] / lba sect or no. / lba [lsb] xx error inform ation
c141-e110-02en 5 - 28 (11) initialize device parameters (x' 91' ) the host sy st em can set t h e num ber of sect ors per t r ack and t h e m a xi m u m head num ber (m axi m um head num ber i s "num ber of heads m i nus 1") per cy l i nder wi t h t h i s com m and. upon receipt of this com m a nd, the device sets the bsy bit of status register and saves the param e ters. then the device clears the bsy bit and generates an interrupt. when t h e sc regi st er i s speci fi ed t o x' 00' , an aborted com m and error i s poste d. ot her th an x ' 0 0 ' is sp ecified , th is co m m an d term in ates n o r m ally. the param e t e rs set by t h i s com m a nd are ret a i n ed even aft e r reset or power save operat i o n regardl e ss of t h e set t i ng of di sabli ng t h e revert i ng t o defaul t set t i ng. in lba m ode the devi ce i gnores t h e l bi t speci fi cat i on and operat e s wi t h t h e chs m ode speci fi cat i on. an accessible area of this com m a nd within head m oving in the lba m ode is always within a default area. it i s recom m e nded t h at t h e host sy st em refers t h e addressabl e user sect ors (t ot al num ber of sect ors) i n word 60 t o 61 of t h e param e t e r i n form at i on by t h e identify device com m a nd. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) 10010001 1f6 h (dh) dv max. head no. 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx number of sectors/track xx at com m and com p l e t i on (i/ o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) d v max. head no. 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (12) identify device (x' e c' ) the host sy st em i ssues t h e identify device com m a nd t o read param e t e r i n form at i on (512 bytes) from the device. upon receipt of this com m a nd, the drive sets the bsy bit of status regi st er and set s requi red param e t e r i n form at i on i n t h e sect or buffer. the devi ce t h en set s t h e drq bi t of t h e st at us regi st er, and generat e s an i n t e rrupt . aft e r t h at , t h e host sy st em reads t h e i n form at i on out of t h e sect or buffer. tabl e 5.5 shows the arrangements and values of the parameter words and the meaning in the buffer.
c141-e110-02en 5 - 29 at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s ) 1f7 h (cm) 11101100 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at command completion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information tabl e 5.5 i nformati on to be read by identify device command (1 of 7) word value description 0 x045a general configuration *1 1 *2 number of cylinders 2 x0000 retired 3 *3 number of heads 4 x0000 retired 5 x0000 retired 6 x003f number of sectors per track 7-9 x000000000000 retired 10-19 C serial number (ascii code) *4 20 x0003 old specifications 21 x0400 buffer size in 512 byte increments 22 x0004 number of ecc bytes transferred at read long or write long command 23-26 C firmware revision (ascii code) *5 27-46 C model number (ascii code) *6 47 x8010 maximum number of sectors per interrupt on read/write multiple command 48 x0000 reserved 49 x2b00 capabilities *7 50 x4000 capabilities 51 x0200 pio data transfer mode *8 52 x0200 single word dma data transfer timing mode 53 x0007 enable/disable setting of words 54-58, 64-70 and 88 *9
c141-e110-02en 5 - 30 tabl e 5.5 informati on to be read by identify device command (2 of 7) word value description 54 (variable) number of current cylinders 55 (variable) number of current head 56 (variable) number of current sectors per track 57-58 (variable) total num ber of current sectors 59 *10 transfer sector count currently set by read/write multiple command 60-61 *11 total number of user addressable sectors (lba mode only) 62 x0000 retired 63 xxx07 multiword dma transfer m ode *12 64 x0003 advance pio transfer m ode support status *13 65 x0078 minimum multiword dma transfer cycle time per word : 120 [ns] 66 x0078 manufacturer's recommended dma transfer cycle time : 120 [ns] 67 x00f0 minimum pio transfer cycle time without flow control : 240 [ns] 68 x0078 minimum pio transfer cycle time with iordy flow control : 120 [ns] 69- 79 x 00 reserved 80 x 003e major version number *14 81 x0015 minor version num ber ata/atapi 5 x3t13 1321d support of rev 1 82 x 346b support of command sets *15 83 x 4108 support of command sets *16 84 x4000 support of command set/feature extension (fixed) 85 x34xx enable/disable command set/feature enabled. *17 86 xxxxx enable/disable command set/feature enabled. *18 87 x4000 default of command set/feature (fixed) 88 xxx3f ultra dma m odes *19 89 x000x time required for security erase unit completion *20 90 x0000 time required for enhanced security erase completion 91 x 00xx current advanced power management value 92 x 0000 reserved 93 xxxxx cblid detection results *21 94 x00xx automatic acoustic management (slow seek mode) *22 95- 127 x 00 reserved 128 x0xxx security status 129- 255 x 00 reserved
c141-e110-02en 5 - 31 tabl e 5.5 i nformati on to be read by identify device command (3 of 7) *1 word 0: general confi gurat i o n bi t 15: 0 = ata devi ce 0 bi t 14-8: vendor speci fi c 0 bi t 7: 1 = rem ovabl e m e di a devi ce 0 bi t 6: 1 = not rem ovabl e cont rol l e r and/ or devi ce 1 bi t 5-1: vendor speci fi c 0 bit 0 : reserv ed 0 *2 num ber of cy l i nders , *3 num ber of heads, *11 tot a l num ber of user addressabl e sect ors (lba mode onl y . ) MPG3102AT m pg3153at m pg3204at m pg3307at m pg3409at *2 x'3fff' ???? *3 x'10' ???? *11 x'01316af0' x'01ca1e70' x'0262d5e0' x'03943ce0' x'04c5abc0' *4 word 10-19: seri al num ber; ascii code (20 charact ers, ri ght -just i fi e d) *5 word 23-26: fi rm ware revi si on; ascii code (8 charact ers, left -just i fi e d) *6 word 27-46: m odel num ber; a s cii co d e (4 0 ch aracters, left-j u stified ), rem a in d e r filled w ith b l an k co d e (x '2 0 ' ) one of t h e fol l owi ng m odel num bers; m pg3102at, m pg3153at, m pg3204at, m pg3307at, m pg3409at * 7 w o rd 4 9 : cap ab ilities bi t 15-14: reserved bi t 13: st andby t i m er val u e 0 = st andby t i m er val u es shal l be m a naged by t h e devi ce bit 1 2 : reserv ed bi t 11: iordy support 1 = support e d bit 1 0 : io rd y in h i b itio n 0 = d i sab l e in h i b itio n bi t 9: lba support 1 = support e d bi t 8: dm a support 1 = support e d bi t 7-0: vendor speci fi c *8 word 51: pio dat a t ransfer m ode bi t 15-8: pio dat a t ransfer m ode x' 04' = pio m ode 4 bi t 7-0: vendor speci fi c *9 word 53: enabl e / d i sabl e set t i ng of word 54-58 ,64-70 and 88 bi t 15-3: reserved bi t 2: enabl e / d i sabl e set t i ng of word 88 1 = enabl e bi t 1: enabl e / d i sabl e set t i ng of word 64-70 1 = enabl e bi t 0: enabl e / d i sabl e set t i ng of word 54-58 1 = enabl e
c141-e110-02en 5 - 32 tabl e 5.5 i nformati on to be read by identify device command (4 of 7) *10 w o rd 59: transfer sector count currently set by read/w r ite multiple com m and bi t 15-9: reserved bit 8 : mu ltiple secto r tran sfer 1 = en ab le bit 7-0: transfer sector count currently set by read/w r ite multiple without i n t e rrupt support s 2, 4, 8 and 16 sect ors. *12 word 63: m ul t i word dm a t r ansfer m ode bi t 15-11: reserved bi t 10: 1 = m u l t i word dm a m ode 2 i s sel ect ed 0 = m u l t i word dm a m ode 2 i s not sel ect ed bi t 9: 1 = m u l t i word dm a m ode 1 i s sel ect ed 0 = m u l t i word dm a m ode 1 i s not sel ect ed bi t 8: 1 = m u l t i word dm a m ode 0 i s sel ect ed 0 = m u l t i word dm a m ode 0 i s not sel ect ed bi t 7-3: reserved bi t 2: 1 = m u l t i word dm a m ode 2 and bel ow are support e d bi t 1: 1 = m u l t i word dm a m ode 1 and bel ow are support e d bi t 0: 1 = m u l t i word dm a m ode 0 i s support e d *13 word 64: advance pio t ransfer m ode support st at us bi t 15-8: reserved bi t 7-0: advance pio t ransfer m ode bi t 1 = 1 m ode 4 bi t 0 = 1 m ode 3 *14 word 80: m a jor versi on num ber bi t 15-6: reserved bi t 5: ata-5 s upport e d = 1 bi t 4: ata-4 s upport e d = 1 bi t 3: ata-3 s upport e d = 1 bi t 2: ata-2 s upport e d = 1 bi t 1: ata-1 s upport e d = 1 bi t 0: undefi ned *15 word 82: support of com m a nd set s bit 1 5 : reserv ed bi t 14: nop com m a nd support e d = 0 bi t 13: read buffer com m and support e d = 1 bi t 12: wri t e buffer com m a nd support e d = 1 bi t 11: wri t e veri fy com m a nd support e d (ol d spec.) = 0 bi t 10: host prot ect ed area feat ure com m and support e d = 1 bi t 9: device reset com m and support e d = 0 bi t 8: service int e rrupt support e d = 0 bi t 7: rel ease int e rrupt support e d = 0 bi t 6: lock ahead support e d = 1 bit 5: w r ite-cache supported = 1 bit 4: packet com m a nd feature set supported = 0 bi t 3: power m a nagem e nt feat ure set support e d = 1 bi t 2: rem ovabl e feat ure set support e d = 0 bit 1: security feature set supported = 1 bi t 0: sm art feat ure set support e d = 1
c141-e110-02en 5 - 33 tabl e 5.5 i nformati on to be read by identify device command (5 of 7) *16 word 83: support of com m a nd set s bit 1 5 : 0 bit 1 4 : 1 bi t 13-5: reserved bi t 4: rem ovabl e me di a st at us not i f i cat i on feat ure set support e d = 0 bi t 3: advanced power m a nagem e nt feat ure set support e d = 1 bi t 2: cfa feat ure set support e d = 0 bi t 1: read/ write dm a queued support e d = 0 bi t 0: download m icrocode com m a nd support e d = 0 *17 w o rd 85: enable/disable com m and set/feature enabled bit 1 5 : reserv ed bi t 14: nop com m a nd enabl e d = 0 bi t 13: read buffer com m a nd enabl e d bi t 12: write buffer com m a nd enabl e d bit 1 1 : reserv ed bit 10: host protected area feature set enabled bi t 9: device reset com m a nd enabl e d = 0 bit 8 : service in terru p t en ab led = 0 bit 7: release interrupt enabled = 0 bi t 6: look-ahead enabl e d bit 5: w r ite cache enabled bit 4: packet com m a nd feature set enabled = 0 bi t 3: power m a nagem e nt feat ure set enabl e d bit 2: rem ovable media feature set enabled = 0 bit 1 : security mo d e featu r e set en ab led bit 0: smart feature set enabled *18 word 86: com m and set / feat ure enabl e d bi t 15-10: reserved bi t 9: 1 = aut om at i c acoust i c m a nagem e nt feat ure set enabl e d bit 8 : 1 = set ma x secu rity exten sio n en ab led b y set ma x set pa ssw o r d bit 7 : reserv ed bi t 6: 0 = set features subcom m a nd requi red t o spi n -up aft e r power-up bi t 5: 0 = power-up in st andby feat ure set enabl e d bi t 4: 0 = rem ovabl e me di a st at us not i f i cat i on feat ure set enabl e d bi t 3: 1 = advanced power m a nagem e nt feat ure set enabl e d bit 2: 0 = cfa feature set enabled bi t 1: 0 = read/ write dm a queued com m a nd support e d bi t 0: 0 = download m icrocode com m and support e d
c141-e110-02en 5 - 34 tabl e 5.5 i nformati on to be read by identify device command (6 of 7) *19 word 88: ul t r a dm a m odes bi t 15-14: reserved bi t 13: 1 = ul t r a dm a m ode 5 i s sel ect ed 0 = ul t r a dm a m ode 5 i s not sel ect ed bi t 12: 1 = ul t r a dma m ode 4 i s select ed 0 = ul t r a dm a m ode 4 i s not sel ect ed bi t 11: 1 = ul t r a dm a m ode 3 i s sel ect ed 0 = ul t r a dm a m ode 3 i s not sel ect ed bi t 10: 1 = ul t r a dm a m ode 2 i s sel ect ed 0 = ul t r a dm a m ode 2 i s not sel ect ed bi t 9: 1 = ul t r a dm a m ode 1 i s sel ect ed 0 = ul t r a dm a m ode 1 i s not sel ect ed bi t 8: 1 = ul t r a dm a m ode 0 i s sel ect ed 0 = ul t r a dm a m ode 0 i s not sel ect ed bi t 7-6: reserved bi t 5: 1 = ul t ra dm a m ode 5 and bel ow are support e d bi t 4: 1 = ul t ra dm a m ode 4 and bel ow are support e d bi t 3: 1 = ul t ra dm a m ode 3 and bel ow are support e d bi t 2: 1 = ul t ra dm a m ode 2 and bel ow are support e d bi t 1: 1 = ul t ra dm a m ode 1 and bel ow are support e d bi t 0: 1 = ul t ra dm a m ode 0 i s support e d *20 word89: ti m e requi red for security erase unit com m and t o com p l e t e . m p g3102at = 0004 h : 8 m i nut es m p g3153at = 0008 h : 16 m i nut es m p g3204at = 0008 h : 16m i nut es m p g3307at = 0010 h : 32 m i nut es m p g3409at = 0010 h : 32 m i nut es *21 word 93: hardware reset resul t . the cont ent s of bi t s 12-0 of t h i s word shal l change onl y during th e execut i on of a hardware reset . bit 1 5 : 0 bit 1 4 : 1 bi t 13: 1 = devi ce det ect ed cblid- above v ih (80-conduct o r cabl e ) 0 = devi ce det ect ed cblid- bel ow v il (40-conduct o r cabl e ) bi t 12-8: device 1 hardware reset resul t . devi ce 0 shal l cl ear t h ese bi t s t o zero. d ev i ce 1 sh all set th ese b its as fo llo w s: bi t 12: 0 = reserved bi t 11: 0 = devi ce 1 di d not assert pdiag- 1 = devi ce 1 assert ed pdiag- bi t 10-9: these bi t s i ndi cat e how devi ce 1 det e rm i n ed th e devi ce num ber. 00 = reserved 01 = a jumper was used 10 = t h e csel si gnal was used 11 = som e ot her m e t hod was used or t h e m e t hod i s unknown bit 8 : 1
c141-e110-02en 5 - 35 tabl e 5.5 i nformati on to be read by identify device command (7 of 7) bi t 7-0: device 0 hardware reset resul t . devi ce 1 shal l clear t h ese bi t s t o zero. d ev i ce 0 sh all set th ese b its as fo llo w s: bit 7 : 0 bi t 6: 0 = devi ce 0 does not respond when devi ce 1 i s sel ect ed 1 = devi ce 0 responds when devi ce 1 i s sel ect ed bi t 5: 0 = devi ce 0 di d not det ect t h e assert i on of dasp- 1 = devi ce 0 det ect ed t h e assert i on of dasp- bi t 4: 0 = devi ce 0 di d not det ect t h e assert i on of pdiag- 1 = devi ce 0 det ect ed t h e assert i on of pdiag- bi t 3: 0 = devi ce 0 fai l e d di agnost i c s 1 = devi ce 0 passed di agnost i c s bi t 2-1: these bi t s i ndi cat e how devi ce 0 det e rm i n ed t h e devi ce num ber. 00 = reserved 01 = a jumper was used 10 = t h e csel si gnal was used 11 = som e ot her m e t hod was used or t h e m e t hod i s unknown bit 0 : 1 *22 word 94: aut om at i c acoust i c m a nagem e nt bi t 15-8: 0 bi t 7-0: current auto m a t i c acoust i c m a nagem e nt valu e
c141-e110-02en 5 - 36 (13) identify device dm a (x' ee' ) w h en th is co m m an d is n o t u sed to tran sfer d ata to th e h o st in d m a m o d e, th is co m m an d fu n ction s in th e sam e w ay as th e id en tify d ev i ce co m m an d . at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) 11101110 1f6 h (dh) dv x x 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at com m and com p l e t i on (i/ o regi st ers contents to be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (14) set features (x' e f' ) the host system issues the set features com m a nd to set param e ters in the features register for the purpose of changing the device features to be executed. for the transfer m ode (feature regi st er = 03), det a i l set t i ng can be done usi ng t h e sect or count regi st er. upon receipt of this com m a nd, the device sets the bsy bit of the status register and saves the param e ters in the features register. then, the device clears the bsy bit, and generates an in terru p t . if t h e val u e i n t h e feat ures regi st er i s not support e d or i t i s i nval i d , t h e devi ce post s an aborted com m and error. tabl e 5.6 l i s t s t h e avai l a bl e values and operational modes that may be set in the features register.
c141-e110-02en 5 - 37 table 5.6 features register values and settable modes feat ures regi st er dri v e operat i on m ode x02 enables the write cache function. x03 specifies the transfer mode. supports pio mode 4, single word dma mode 2, and multiword dma mode regardless of sector count register contents. x04 no operation. x05 enable the advanced power management function. x33 no operation. x42 enable automatic acoustic management feature set x54 no operation. x55 disables read cache function. x66 disables the reverting to power-on default settings after software reset. x77 no operation. x81 no operation. x82 disables the write cache function. x84 no operation. x85 disable the advanced power management function. x88 no operation. x89 no operation. xaa enables the read cache function. xab no operation. xbb specifies the transfer of 4-byte ecc for read long and write long commands. xc2 disable automatic acoustic management feature set xcc enables the reverting to power-on default settings after software reset.
c141-e110-02en 5 - 38 at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s ) 1f7 h (cm) 11101111 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx or transfer mode [see table 5.6] at command completion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information th e h o s t sets x ' 0 3 ' to th e featu r es reg i ster. by issu in g th is co m m an d w ith settin g a v alu e to th e sector count regi st er, t h e t r ansfer m ode can be sel ect ed. upper 5 bi t s of t h e sect or count regi st er defi nes t h e tr ansfer t y p e and l ower 3 bi t s speci fi es t h e bi nary m ode val u e. however, the idd can operate with the pio transfer m ode 4 and m u ltiword dma transfer m ode 2 regardless of reception of the set features com m a nd for transfer m ode setting. the idd support s fol l owi ng val u es i n t h e sect or count regi st er val u e. if ot her val u e t h an bel o w i s speci fi ed, an aborted com m and error i s post e d. pio defaul t t ransfer m ode 00000 000 (x00) pio fl ow cont rol t ransfer m ode x 00001 000 (x08: m ode 0) 00001 001 (x09: m ode 1) 00001 010 (x0a: m ode 2) 00001 011 (x0b: m ode 3) 00001 100 (x0c: m ode 4) m u l t i word dm a t ransfer m ode x 00100 000 (x20: m ode 0) 00100 001 (x21: m ode 1) 00100 010 (x22: m ode 2) ul t ra dm a t ransfer m ode x 01000 000 (x40: m ode 0) 01000 001 (x41: m ode 1) 01000 010 (x42: m ode 2) 01000 011 (x43: m ode 3) 01000 100 (x44: m ode 4) 01000 101 (x45: m ode 5)
c141-e110-02en 5 - 39 subcom m a nd code 42h al l ows t h e host t o enabl e t h e aut om at i c acoust i c m a nagem e nt feat ure set . to enabl e t h e aut om at i c acoust i c m a nagem e nt feat ure set , t h e host wri t e s t h e sect or count regist er wi t h t h e request ed aut o m a t i c acoust i c m a nagem e nt l e vel and execut e s a set features com m a nd wi t h subcom m a nd code 42h. the acoust i c m a nagem e nt l e vel i s sel ect ed on a scale from 01h t o feh. fol l owi ng t a bl e shows t h e acoust i c m a nagem e nt l e vel val u es. enabl i ng or di sabli ng of t h e aut om at i c acoust i c m a nagem e nt feature set , and t h e current au to m atic aco u stic m an ag em en t lev el settin g w ill b e p r eserv ed b y th e d ev i ce across all fo rm s o f reset , i . e., power on, hardware, and software reset s. aut om at i c m a nagem e nt l e vel s level sector count val u e reserved ffh maximum performance c0h - feh m i n i m um acoust i c em anation level 80h - bfh ret i r ed 01h - 7fh vendor specific (maximum performance) 00h subcom m a nd code c2h di sabl es t h e aut om at i c acoust i c m a nagem e nt feat ure set . devi ces t h at i m pl em ent set features subcom m a nd 42h are not requi red t o i m pl em ent subcom m a nd c2h. if d ev i ce su ccessfu lly co m p letes ex ecu tio n o f th is su b co m m an d , th en th e aco u stic b eh av i o r o f th e devi ce shal l be vendor-speci fi c, and t h e devi ce ret u rn zeros i n bi t s 0-7 of word 94 and bi t 9 of word 86 of t h e identify device dat a . (15) set multiple mode (x' c 6' ) this com m a nd enables the device to perform the read multiple and w r ite multiple com m a nds. the bl ock count (num ber of sect ors i n a bl ock) for t h ese com m a nds are al so speci fi ed by the set multiple mode com m a nd. the num ber of sectors per block is written into the sector count register. the idd supports 2, 4, 8 and 16 (sect ors) as t h e bl ock count s. upon receipt of this com m a nd, the device sets the bsy bit of the status register and checks the content s of t h e sect or count regi st er. if t h e cont ent s of t h e sect or count regi st er i s val i d and i s a support e d bl ock count , t h e val u e i s st ored for al l subsequent read m u ltiple and write multiple com m a nds. execution of these com m ands is then enabled. if the value of the sector count regi st er i s not a support e d bl ock count , an aborted com m and error i s post e d and t h e read multiple and w r ite multiple com m ands are disabled. if t h e cont ent s of t h e sect or count regi st er i s 0 when t h e set m u ltiple m ode com m and i s issued, the read multiple and w r ite multiple com m ands are disabled. w h en the set multiple mode com m a nd operation is com p leted, the device clears the bsy bi t and generat e s an i n t e rrupt .
c141-e110-02en 5 - 40 at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s ) 1f7 h (cm) 11000110 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx sector count/block xx at command completion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx sector count/block error information aft e r power-on or aft e r hardware reset , t h e read m u ltiple and write m u ltiple com m a nd operat i on are di sabl ed as t h e defaul t m ode. regarding software reset, the m ode set prior to software reset is retained after software reset. th e p aram eters fo r th e m u ltip le co m m an d s w h i ch are p o s ted to th e h o s t system w h en th e identify device command is i ssued are l i s t e d bel ow. see subsect i on 5.3.2 for t h e identify device com m a nd. word 47 = 8010: word 59 = 0000: = 01xx: m a xi m u m num ber of sect ors t h at can be t r ansferred per i n t e rrupt by t h e read m u ltiple and write m u ltiple com m ands are 16 (fi xed). the read multiple and w r ite multiple com m a nds are disabled. the read multiple and w r ite multiple com m a nds are enabled. "xx" i ndi cat es t h e current set t i ng for num ber of sect ors t h at can be t r ansferred per i n t e rrupt by t h e read m u ltiple and write multiple com m a nds. e.g. 0110 = bl ock count of 16 has been set by t h e set m u ltiple m ode c o mma n d . (16) execute device diagnostic (x' 90' ) thi s com m a nd perform s an i n t e rnal di agnost i c t e st (sel f-dia gnosi s) of t h e device. thi s com m a nd usually sets the drv bit of the drive/head register is to 0 (however, the dv bit is not checked). if t wo devi ces are present , bot h devi ces execut e sel f-dia gnosi s.
c141-e110-02en 5 - 41 if devi ce 1 i s present : bot h devi ces shal l execut e sel f-dia gnosi s. the device 0 waits for up to 5 seconds until device 1 asserts the pdiag- signal. if t h e devi ce 1 does not assert t h e pdiag- si gnal but i ndi cat es an error, t h e devi ce 0 shal l append x' 80' t o i t s own di agnost i c st at us. the devi ce 0 cl ears t h e bsy bi t of t h e st at us regi st er and generat e s an i n t e rrupt . (the device 1 does not generat e an i n t e rrupt .) a di agnost i c st at us of t h e devi ce 0 i s read by t h e host sy st em . when a di agnost i c fai l u re of the device 1 is detected, the host system can read a status of the device 1 by setting the dv bit (selecting the device 1). when devi ce 1 i s not present : the devi ce 0 post s onl y t h e resul t s of i t s own sel f-di a gnosi s. the devi ce 0 cl ears t h e bsy bi t of t h e st at us regi st er, and generat e s an i n t e rrupt . table 5.7 lists the diagnostic code written in the error register which is 8-bit code. if t h e device 1 fai l s t h e sel f-dia gnosi s, t h e devi ce 0 "ors" x' 80' wi t h i t s own st at us and set s t h at code to the error register. table 5.7 d i agnosti c code code resul t of di agnost i c x00 x01 x02 x03 x04 x05 x06 x8x mechanical failure no error detected hardware error buffer failure sram failure sa read failure power on cal i b rat i on fai l u re fai l ure of device 1 at com m a nd i ssuance (i/ o regi st ers set t i ng cont ents) 1f7 h (cm) 10010000 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx
c141-e110-02en 5 - 42 at com m and com p l e t i on (i/ o regi st ers cont ent s t o be read) 1f7 h (st) status information 1f6 h (dh) 00 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) 00 00 01 h 01 h diagnostic code (17) form at track (x' 50' ) upon receipt of this com m a nd, the device sets the drq bit and waits the com p letion of 512-byte form at param e ter transfer from the host system . after com p letion of transfer, the device clears the drq bi t s , set s t h e bsy bi t . however t h e devi ce does not perform form at operat i on, but t h e dri v e cl ears t h e bsy bi t and generat e s an i n t e rrupt soon. when t h e com m a nd execut i on com p l e t e s, t h e device cl ears t h e bsy bi t and generat e s an i n t e rrupt . the drive supports this com m a nd for keep the com p atibility with previous drive only. (18) read long (x' 22' or x' 23' ) th is co m m an d o p erates sim ilarly to th e rea d secto r (s) co m m an d ex cep t th at th e d ev i ce transfers the data in the requested sector and the ecc bytes to the host system . the ecc error correct i on i s not perform ed for t h i s com m and. thi s com m and i s used for checki ng ecc funct i o n by com b i n i ng wi t h t h e write long com m a nd. the read long com m a nd support s onl y si ngl e sect or operat i on. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) 0010001r 1f6 h (dh) l dv head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) cy l i nder no. [m sb] / lba cy l i nder no. [lsb] / lba sect or no. / lba [lsb] num ber of sect ors t o be t r ansferred xx r = 0 or 1
c141-e110-02en 5 - 43 at com m and com p l e t i on (i/ o regi st ers cont ent s t o be read) 1f7 h (st) status information 1f6 h (dh) l dv head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) cy l i nder no. [m sb] / lba cy l i nder no. [lsb] / lba sect or no. / lba [lsb] 00 (*1) error information *1 if the com m a nd is term inated due to an error, this register indicates 01. (19) write long (x' 32' or x' 33' ) th is co m m an d o p erates sim ilarly to th e rea d secto r (s) co m m an d ex cep t th at th e d ev i ce writes th e d ata an d th e ecc b ytes tran sferred fro m th e h o s t system to th e d i sk m ed i u m . th e devi ce does not generat e ecc by t e s by i t sel f. the write long com m a nd support s onl y si ngl e sector operat i on. this com m a nd is operated under the following conditions: the com m a nd i s i ssued i n a sequence of t h e read long or write long (t o t h e sam e address) com m a nd i ssuance. (write long com m a nd can be cont i nuousl y i ssued aft e r t h e read long com m a nd.) if above condition is not satisfied, the com m a nd operation is not guaranteed. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) 0011001r 1f6 h (dh) l dv head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) cy l i nder no. [m sb] / lba cy l i nder no. [lsb] / lba sect or no. / lba [lsb] num ber of sect ors t o be t r ansferred xx r = 0 or 1 at com m and com p l e t i on (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) l dv head no. /lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) cy l i nder no. [m sb] / lba cy l inder no. [lsb] / lba sector no. / lba [lsb] 00 (*1) error information *1 if the com mand is terminated due to an error, this register indicates 01.
c141-e110-02en 5 - 44 (20) read buffer (x' e 4' ) the host system can read the current contents of the sector buffer of the device by issuing this com m a nd. upon receipt of this com m a nd, the device sets the bsy bit of status register and sets up t h e sector buffer for a read operat i on. then t h e devi ce set s t h e drq bi t of st at us regi st er, cl ears t h e bsy bi t , and generat e s an i n t e rrupt . aft e r t h at , t h e host sy st em can read up t o 512 by t e s of data from the buffer. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) 11100100 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at com mand completion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (21) write buffer (x' e 8' ) the host sy st em can overwri t e t h e cont ent s of t h e sect or buffer of t h e devi ce wi t h a desi red dat a pattern by issuing this com m a nd. upon receipt of this com m a nd, the device sets the bsy bit of the status register. then the device sets the drq bit of status register and clears the bsy bit when the device is ready to receive the data. after that, 512 bytes of data is transferred from the host and t h e devi ce wri t e s th e dat a t o t h e sect or buffer, t h en generat e s an i n t e rrupt . at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h ( c m ) 11101000 1f6 h (dh) dv x x 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx
c141-e110-02en 5 - 45 at com m and com p l e t i on (i/ o regi st ers cont ent s t o be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (22) idle (x' 97' or x' e3' ) upon receipt of this com m a nd, the device sets the bsy bit of the status register, and enters the i d l e m ode. then, t h e devi ce cl ears t h e bsy bi t , and generat e s an i n t e rrupt . the devi ce generat e s an in terru p t ev en if th e d ev i ce h as n o t fu lly en tered th e id le m o d e. if th e sp in d l e o f th e d ev i ce is al ready rot a t i ng, t h e spi n -up sequence shal l not be i m pl em ent e d. if t h e cont ent s of t h e sect or count regi st er i s ot her t h an 0, t h e aut o m a t i c power-down funct i on i s enabled and the tim er starts countdown im m e diately. w h en the tim er reaches the specified tim e, t h e devi ce ent e rs t h e st andby m ode. if t h e cont ent s of t h e sect or count regi st er i s 0, t h e aut o m a t i c power-down funct i on i s disabl ed. enabling the autom a tic power-down function m eans that the device autom a tically enters the st andby m ode aft e r a cert a i n peri od of t i m e. when t h e devi ce ent e rs t h e i d l e m ode, t h e t i m er st art s count down. if any com m a nd i s not i ssued whi l e t h e t i m er i s count i ng down, t h e devi ce autom a tically enters the standby m ode. if any com m and is issued while the tim er is counting down, the tim er is initialized and the com m and is executed. the tim er restarts countdown after com p letion of the com m a nd execution. the period of t i m er count i s set dependi ng on t h e val u e of t h e sect or count regi st er as shown bel ow. sector count regi st er val u e poi nt of t i m er 0 [ x' 00' ] d i s able of timer 1 t o 240 [x' 01' t o x'f0'] (value 5) seconds 241 t o 251 [x' f 1' t o x' fb' ] (val ue C 240) 30 m inutes 252 [x'fc'] 21 minutes 253 [x'fd'] 8 hours 254 t o 255 [x' f e' t o x' ff' ] 21 m i nut es 15 seconds
c141-e110-02en 5 - 46 at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s ) 1f7 h (cm) x'97' or x'e3' 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx period of timer xx at command completion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (23) idle im m e diate (x' 95' or x' e1' ) upon receipt of this com m a nd, the device sets the bsy bit of the status register, and enters the i d l e m ode. then, t h e devi ce cl ears t h e bsy bi t , and generat e s an i n t e rrupt . thi s com m and does not support t h e aut o m a t i c power-down funct i on. at command issuance (i/o registers setting contents) 1f7 h (cm) x'95' or x'e1' 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at command completion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information
c141-e110-02en 5 - 47 (24) standby (x' 96' or x' e2' ) upon receipt of this com m a nd, the device sets the bsy bit of the status register and enters the st andby m ode. the devi ce t h en cl ears t h e bsy bi t and generat e s an i n t e rrupt . the devi ce generates an interrupt even if the device has not fully entered the standby m ode. if the device has al ready spun down, t h e spi n -down sequence i s not i m pl em ent e d. if t h e cont ent s of t h e sect or count regi st er i s ot her t h an 0, t h e aut o m a t i c power-down funct i on i s enabl e d and t h e ti m er st art s count down when t h e devi ce ret u rns t o i d l e m ode. w h en the tim er value reaches 0 (passed a specified tim e), the device enters the standby m ode. if t h e cont ent s of t h e sect or count regi st er i s 0, t h e aut o m a t i c power-down funct i on i s disabl ed. under t h e st andby m ode, t h e spi ndl e m o t o r i s st opped. thus, when t h e com m a nd i nvol vi ng a seek such as the read sector(s) com m a nd is received, the device processes the com m a nd after dri v i ng t h e spi ndl e m o t o r. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) x'96' or x'e2' 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx period of timer xx at com m and com p l e t i on (i/ o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) dv x x 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (25) standby im m e diate (x' 94' or x' e0' ) upon receipt of this com m a nd, the device sets the bsy bit of the status register and enters the st andby m ode. the devi ce t h en cl ears t h e bsy bi t and generates an interrupt. this command does not support the automatic power-down sequence.
c141-e110-02en 5 - 48 at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s ) 1f7 h (cm) x'94' or x'e0' 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at command completion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (26) sleep (x' 99' or x' e6' ) th is co m m an d is th e o n ly w ay to m ak e th e d ev i ce en ter th e sleep m o d e. upon receipt of this command, the device sets the bsy bit of the status register and enters the sl eep m ode. the devi ce t h en cl ears t h e bsy bi t and generat e s an i n t e rrupt . the device generat e s an in terru p t ev en if th e d ev i ce h as n o t fu lly en tered th e sleep m o d e. in the sleep m ode, the spindle m o tor is stopped and the ata interface section is inactive. all i/o regist er out put s are i n high-im pedance st at e. the only way to release the device from sleep m ode is to execute a software or hardware reset. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) x'99' or x'e6' 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx
c141-e110-02en 5 - 49 at com m and com p l e t i on (i/ o regi st ers cont ent s t o be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (27) check power m ode (x' 98' or x' e5' ) the host checks t h e power m ode of t h e devi ce wi t h t h i s com m a nd. the host sy st em can confi r m t h e power save m ode of t h e devi ce by anal y z i ng t h e cont ent s of t h e sect or count and sect or regi st ers. the devi ce set s t h e bsy bi t and set s t h e fol l owi ng regi st er val u e. aft e r t h at , t h e devi ce cl ears t h e bsy bi t and generat e s an i n t e rrupt . power save mode sector count register ? duri ng m ovi ng t o st andby m ode ? st andby m ode ? duri ng ret u rni ng from t h e st andby m ode x'00' ? idle mode x'80' ? active mode x'ff' at command issuance (i/o registers setting contents) 1f7 h (cm) x'98' or x'e5' 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx
c141-e110-02en 5 - 50 at com m and com p l e t i on (i/ o regi st ers cont ent s t o be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx x'00' or x'ff' error information (28) sm art (x' b 0) this com m a nd perform s operations for device failure predictions according to a subcom m a nd speci fi ed i n t h e fr regi st er. if t h e val u e speci fi ed i n t h e fr regi st er i s support e d, t h e abort e d com m a nd error i s post e d. it i s necessary for t h e host t o set t h e key s (cl = 4fh and ch = c2h) i n t h e cl and ch regi st ers prior to issuing this com m a nd. if the keys are set incorrectly, the aborted com m and error is post e d. when t h e fai l u re predi c t i on feat ure i s di sabl ed, t h e abort e d com m and error i s post e d i n response t o subcom m a nds ot her t h an sm art enabl e operat i ons (fr regi st er = d8h). when t h e fai l u re predi c t i on feat ure i s enabl e d, t h e devi ce col l ect s or updat e s several i t e m s t o forecast failures. in the following sections, note that the values of item s collected or updated by the device to forecast failures are referred to as attribute values.
c141-e110-02en 5 - 51 table 5.8 features register values (subcommands) and functions (1/2) features resister function xd0 sm art read at t r i but e val u es: a device that received this subcom m a nd asserts the bsy bit and saves all the updat e d at t r i but e val u es. the devi ce t h en cl ears t h e bsy bi t and t r ansfers 512-by t e attrib u t e v alu e in fo rm atio n to th e h o s t. * for i n form at i on about t h e form at of t h e at t r i but e val u e i n form at i on, see tabl e 5.9. xd1 sm art read at t r i but e threshol ds: thi s subcom m a nd i s used t o t r ansfer 512-by t e i n surance fai l u re t h reshol d val u e dat a to th e h o s t. * for information about the format of the insurance failure threshold value data, see table 5.10. xd2 sm art enabl e -di s abl e at t ri but e aut osave: thi s subcom m a nd i s used t o enabl e (sc regi st er 1 00h) or di sabl e (sc regi st er = 00h) the setting of the autom a tic saving feature for the device attribute data. the settin g is m ain tained ev ery tim e th e d ev i ce is turn ed o ff an d th en o n . w h en th e autom a tic saving feature is enabled, the attribute values are saved after 15 m i nutes passed si nce t h e previ ous savi ng of t h e at t r i but e val u es. however, i f t h e fai l u re p r ed ictio n featu r e is d i sab l ed , th e attrib u t e v alu es are n o t au to m atically sav ed . w h en the device receives this subcom m a nd, it asserts the bsy bit, enables or disables the autom a tic saving feature, then clears the bsy bit. xd3 sm art save at t r i but e val u es: w h en the device receives this subcom m a nd, it asserts the bsy bit, saves device attrib u t e v alu e d ata, then clears th e bsy b it. xd4 smart execute off-line im m e diate/execute self test: the device that received these subcom m a nds shall execute off-line data collection or sel f test , or devi ce shal l abort current sel f test . the set t i ng of sn regi st er i s descri bed as fol l owi ng. off-l i n e dat a col l ect i on: (sn regi st er = 00h) sel f test funct i ons: - qui ck test C off-l i n e m ode (sn regi st er = 01h) - qui ck test C capt i v e m ode (sn regi st er = 81h) - com p rehensi v e test C off-l i n e m ode (sn regi st er = 02h) - com p rehensi v e test C capt i v e m ode (sn regi st er = 82h) - sel f test st op (sn regi st er = 7fh) the device that received subcom m a nd (sn register is described 00h, 01h or 02h) sh all ex ecu te o ff-lin e d a ta co llectio n o r self test after asserts th e bsy b it an d clears it. the device that received subcom m a nd (sn register is described 81h or 82h) shall ex ecu te self test after assert th e bsy b it, th en clears th e bsy b it after co m p letes these com m a nd process. the device that received subcom m a nd (sn register is described 7fh) shall assert the bsy bi t . when t h e devi ce i s i n process of perform i ng sel f test or off-l i n e dat a col l ect i on, i t shoul d abort t h e current self test or off-line data collection, then clears the bsy bit.
c141-e110-02en 5 - 52 table 5.8 features register values (subcommands) and functions (2/2) xd5 sm art read loggi ng dat a : thi s subcom m a nd i s used t o t ransfer 512-by t e l oggi ng dat a t o t h e host . the set t i ng of sn regi st er i s descri bed as fol l owi ng. log sect or address 01h (sc regi st er 01h): sm a rt error log (see tabl e 5.11) 06h (sc regi st er 01h): sm a rt sel f test log (see tabl e 5.12) 80-9fh: host vendor speci fi c w h en the device receives these subcom m a nds, it asserts the bsy bit and transfers 512-by t e l ogging dat a t o t h e host , t h en cl ears t h e bsy bi t . xd6 sm art wri t e loggi ng dat a : thi s subcom m a nd i s used t o t ransfer 512-by t e l oggi ng dat a from t h e host , and saves these data on the m e dia. log sect or address 80-9fh: host vendor speci fi c wh en the device receives this subcom m a nd, it receives 512-byte logging data from t h e host , and assert s th e bsy bi t and saves 512-by t e dat a on t h e m e di a, t h en cl ears th e bsy b it. xd8 sm art enabl e operat i ons: th is su b co m m an d enab les th e failu re p r ed ictio n featu r e. th e settin g is m ain tain ed even when t h e devi ce i s t u rned off and t h en on. w h en the device receives this subcom m a nd, it asserts the bsy bit, enables the failure prediction feature, then clears the bsy bit. xd9 sm art di sabl e operat i ons: th is su b co m m an d d i sab l es th e failure p r ed ictio n featu r e. th e settin g is m ain tained even when t h e devi ce i s t u rned off and t h en on. w h en the device receives this subcom m a nd, it asserts the bsy bit, disables the failure prediction feature, then clears the bsy bit. xda sm art ret u rn st at us: w h en the device receives this subcom m a nd, it asserts the bsy bit and saves the current device attribute values. then the device com p ares the device attribute values with insurance failure threshold values. if there is an attribute value exceeding the threshold, f4h and 2ch are loaded into the cl and ch registers. if there are no attribute values exceeding the thresholds, 4fh and c2h are loaded into the cl and ch registers. after the settings for the cl and ch registers have been determ ined, the device clears the bsy bit. x d b s ma rt en ab le/d isab le a u t o m atic o ff-lin e: the device that receives this subcom m a nd enables (sc register 1 00h) or di sabl es (sc register = 00h) autom a tic off-line data collection. the condition is m a intained even when t h e devi ce i s t u rned off and t u rned on. w h en th e failu re p r ed ictio n featu r e an d au to m atic o ff-lin e d ata co llectio n are enabl e d, an off-l i n e dat a col l ect i on shal l be perform ed regardl e ss of host i ssued com m a nd aft e r m o re t h an 4 hours passed si nce power-on or t h e previ ous off-l i n e d a ta co llectio n . w h en the device receives this subcom m a nd, it asserts the bsy bit, enables or d i sab l es au to m atic off-lin e d ata collectio n , th en clears th e bsy b it.
c141-e110-02en 5 - 53 the host m u st regul arl y i ssue t h e sm art read at t r i but e val u es subcom m a nd (fr regi st er = d0h), sm art save at t r i but e val u es subcom m a nd (fr regi st er = d3h), or sm art ret u rn st at us subcom m a nd (fr regi st er = dah) t o save t h e devi ce at t r i but e val u e dat a on a m e di um . al t e rnati v e, t h e devi ce m u st i ssue t h e sm art enabl e -di sabl e at t r i but e aut osave subcom m a nd (fr regi st er = d2h) t o use a feat ure whi ch regul arl y save t h e devi ce at t r i but e val u e dat a t o a m e dium . th e h o st can p r ed ict failu res in th e d ev i ce b y p eriod i cally issuin g th e sma r t return statu s subcom m a nd (fr regi st er = dah) t o reference t h e cl and ch regi st ers. if an at t ri but e val u e i s bel ow t h e i n surance fai l u re t h reshol d val u e, t h e devi ce i s about t o fai l or t h e device is nearing the end of it life . in this case, the host recom m e nds that the user quickly backs up t h e dat a . at com m a nd issuance (i-o registers setting contents) 1f7 h (cm) 10110000 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) key (c2h) key (4fh) xx xx subcommand at com mand completion (i-o registers setting contents) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) key -fai l u re predi c t i on st at us (c2h-2ch) key-failure prediction status (4fh-f4h) xx xx error information
c141-e110-02en 5 - 54 the at t r i but e val u e i n form at i on i s 512-by t e dat a ; t h e form at of t h i s dat a i s shown i n tabl e 5.9. the host can access this data using the smart read attribute values subcom m a nd (fr register = d0h). the i n surance fai l u re t h reshol d val u e dat a i s 512-by t e dat a ; t h e form at of t h i s dat a i s shown in table 5.10. the host can access this data using the smart read attribute thresholds subcom m a nd (fr regi st er = d1h). table 5.9 device attribute data structure byte (h ex ) d escrip tio n 00 01 dat a structure revision number *1 02 at t ri but e id num ber *2 03 04 status flag *3 05 norm a l i zed at t r i but e val u es *4 06 w orst ever normalized *5 07 to 0c raw at t ribute values *6 0d 1 st attrib u t e reserved 0e to 169 2 nd to 3 0 th attrib u t e reserved (each attribute form at is the sam e as 1 st attrib u t e.) 16a off-l i ne data collection status *7 16b sel f test execution status byte *8 16c 16d off-line data collection executing tim es (sec) 16e reserved 16f o ff-lin e d ata co llectio n o ff-lin e d a ta co llectio n cap ab ility * 9 170 171 smar t cap ab ility flag * 1 0 172 drive error logging capability *11 173 sel f test failure checkpoint 174 q u ick test completion time (min) *12 175 co m prehensive test completion time (min) *13 176 to 181 reserved 182 to 1fe vendor uni que 1ff check sum *14
c141-e110-02en 5 - 55 table 5.10 warranty failure threshold data structure byte (h ex ) d escrip tio n 00 01 data structure revision number *1 02 attribute id number *2 03 04 attribute threshold *15 05 06 07 to 0c 0d 1 st dri v e t h reshol d reserved 0e to 169 2 nd to 3 0 th dri v e t h reshol d reserved (each threshold format is the same as 1 st drive threshold.) 16a to 17b reserved 17c to 1fe vendor unique 1ff check sum *1 dat a st ruct ure revi si on num ber it indicates the revision number of device attribute and warranty failure threshold. they will have the same data structure revision number.
c141-e110-02en 5 - 56 *2 at t ri but e id the at t r i but e id i s defi ned as fol l ows: attribute id (dec) description 0 (indicates unused attribute data) 1 r ead error rate 2 throughput performance 3 spin up time 4 number of times the spindle motor is activated 5 number of alternative sectors 6 read channel margin (not supported) 7 s eek error rate 8 seek time performance 9 power-on time 10 number of retries made to activate the spindle motor 1 1 number of retries to calibration 12 number of turn on/off times 13 t o 198 reserved 199 ultra ata crc error rate 200 write error rate 201 t o 255 (vendor unique) *3 st at us fl ag bit description 0 if this bit is set to 1, it indicates the attribute is guaranteed for normal operation when an attribute value exceeds the threshold. 1 if this bit is set to 1 (0), it indicates the attribute is updated only by on-line test (off-line test). 2 if this bit is set to 1, it indicates a performance attribute. 3 if this bit is set to 1, it indicates an error-rate attribute. 4 if this bit is set to 1, it indicates an event count attribute. 5 if this bit is set to 1, it indicates the attribute shall be collected and saved even if the failure prediction feature is disabled. 6 t o 15 reserved bits
c141-e110-02en 5 - 57 *4 norm a l i zed at t r i but e val u e the current attribute value is the norm a lized raw attribute data. the value varies between 01h and 64h. the closer the value gets to 01h, the higher the possibility of a failure. the device com p ares the attribute values with thresholds. w h en the attribute values are larger than the th resho l d s, th e d ev i ce is o p eratin g n o r m ally. *5 w o rst ever norm a lized thi s i s t h e worst at t r i but e val u e am ong t h e at t r i but e val u es col l ect ed t o dat e . thi s val u e indicates the state nearest to a failure so far. *6 raw at t r i but e val u e raw attrib u t es d ata is retain ed . *7 off-l i n e dat a col l ect i on st at us val u es descri pt i o n 00h or 80h off-l i n e dat a col l ection is not started. 01h or 81h reserved 02h or 82h off-l i n e dat a col l ection has been completed without error. 03h or 83h reserved 04h or 84h off-l i n e dat a col l ection has been suspended by an interrupt command from the host. 05h or 85h off-l i n e dat a col l ection has been aborted by an interrupt command from the host. 06h or 86h off-l i n e dat a col l ection has been aborted with a fatal error. (not used) 40h to 7fh c0h to ffh vendor unique (not used) 07h t o 3fh 87h t o bfh reserved if bit [7] is 1 , it in d i cates th at au to m atic off-lin e d ata collectio n fu n ction is en ab led . *8 sel f test execut i on st at us by t e [16bh] bit 0 - 3 : self test rem ain tim e. th e v alu es in th ese b its in d i cate the rem ain in g p ercen tag e (0 % - 9 0 %) o f self test u n til com ple t i on by 0h-9h. bi t 4-7: sel f test execut i on st at us 00h: self test has been com p leted norm a lly. otherwise self test has not perform ed. 01h: sel f test has been i n t e rrupt ed by host . 02h: sel f test has been i n t e rrupt ed by t h e soft / h ard reset from t h e host .
c141-e110-02en 5 - 58 03h: sel f test has been abort e d for a fi nal error. 04h: self test has been com p leted abnorm a lly for an unknown m eaning. 05h: self test has been com p leted abnorm a lly by w r ite/read test. 06h: self test has been com p leted abnorm a lly by servo analysis. 07h: self test has been com p leted abnorm a lly by read scan test 08h-0eh: reserved 0fh: sel f test i s bei ng perform ed. * 9 o ff-lin e d ata co llectio n cap ab ility [1 6 f h ] bit d escrip tio n 0 if th is b it is set to 1 , it in d i cates sma r t ex ecu te o ff-lin e im m ediate subcommand is supported. (fr register = d4) 1 vendor uni que 2 if th is b it is set to 1, it indicates off-line data collection being aborted when a new command is received. 3 if th is b it is set to 1, it indicates smart off-line read scanning is supported. 4 if t h is bit is set to 1, it indicates smart self test is supported. 5 t o 7 reserved bits *10 smart capability flag [170-171h] bit d escrip tio n 0 if th is b it is set to 1, it indicates the attribute data is saved to the media before the drive enters power save mode. 1 if th is b it is set to 1, it indicates the device saves the attribute automatically according to fixed operation. 2-15 reserved bits *11 drive error logging capability [172h] bit d escrip tio n 0 if t h is bit is set to 1, it indicates the drive error logging is supported. 1 t o 15 reserved bits *12 qui ck test com p l e t i on t i m e [m i nut es] this value indicates the processing tim e of the quick test (off-line m ode). *13 com p rehensive test completion time [minutes]
c141-e110-02en 5 - 59 thi s val u e i ndi cat es t h e processi ng t i m e of t h e com p rehensi v e test (off-l i n e m ode). *14 check sum twos com p l e m e nt of t h e l ower by t e , obt ai ned by addi ng 511-by t e dat a one by at a t i m e from t h e begi nni ng. *15 at t ri but e t h reshol d th e lim it o f a v a ryin g attrib u t e v a lu e. th e h o st co m p ares th e attrib u t e v a lu es with th e th resho l d s to id en tify a failu re. tabl e 5.11 error l oggi ng data structure address (hex) descri pt i o n 00 sm art error l ogging version 01h 01 index poi nt er of latest error data structure 02 to 31 reserved 32 devi ce cont rol register 33 features register 34 sect or count register 35 sect or num ber register 36 cy l inder low register 37 cy l inder high register 38 dri v e/head register 39 com m and register 3a t o 3d com m a nd dat a structure el apsed t i m e from power-on [m s] 3e reserved 3f error register 40 sect or count regi st er 41 sect or num ber regi st er 42 cy l i nder low register 43 cy l i nder high register 44 dri v e/ head register 45 st at us regi st er 46 to 58 vendor unique 59 state 5a 5b error log data stucture 1 error data structure cu m u lativ e elap sed tim e [h ] 5c to 1c3 error l og dat a structure 2-5 data structure sam e as error log data structure 1 1c4 1c5 total error count 1c6 to 1fe reserved 1ff check sum
c141-e110-02en 5 - 60 *16 com m a nd dat a st ruct ure it indicates that the device has received structure of the com m a nd when the drive occurs the error. *17 error data structure it indicates that structure of the ata taskfile register which the drive occurs the error. *18 tot a l error count it i ndi cat es t h at t h e to t a l count of t h e error regi st ered i n t h e error l og. *19 check sum twos com p l e m e nt of t h e l ower by t e , obt ai ned by addi ng 511-by t e dat a one by at a t i m e from t h e begi nni ng.
c141-e110-02en 5 - 61 (29) flush cache (xe7) this com m a nd is use by the host to request the device to flush the write cache. if the write cache is to be flushed, all data cached shall be written to the m e dia. the bsy bit shall rem a in set to one until all data has been successfully written or an error occurs. the device should use all error recovery m e thods available to ensure the data is written successfully. the flushing of write cache m a y t a ke several seconds t o com p l e t e dependi ng upon t h e am ount of dat a t o be fl ushed and t h e success of t h e operat i on. note - thi s com m a nd m a y t a ke l onger t h an 30 s t o com p l e t e . if t h e com m a nd i s not support e d, t h e devi ce shal l set t h e abrt bi t t o one. an unrecoverabl e error encountered during execution of writing data results in the term ination of the com m and and t h e com m and bl ock regist ers contai n t h e sect or address of t h e sect or where t h e fi rst unrecoverable error occurred. the sector is rem oved from the cache. subsequent flush cache com m a nds continue the process of flushing the cache. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) x'e7' 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at com m and com pletion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error inform ation
c141-e110-02en 5 - 62 (30) security disable password (f6h) this com m a nd invalidates the user password already set and releases the lock function. the host t r ansfers t h e 512-by t e dat a shown i n tabl e 1.1 t o t h e devi ce. the devi ce com p ares t h e user password or m a st er password i n t h e t r ansferred dat a wi t h t h e user password or m a st er password al ready set , and rel eases t h e lo ck funct i on i f t h e passwords are t h e sam e . al t hough t h i s com m a nd i nvali d at es t h e user password, t h e m a st er password i s ret a i n ed. to recover t h e m a st er password, i ssue t h e security set password com m and and reset t h e user password. if t h e user password or m a st er password t r ansferred from t h e host does not m a t c h, t h e abort e d com m a nd error is returned. issui ng t h i s com m a nd whi l e i n locked m ode or frozen m ode ret u rns t h e abort e d com m a nd error. (the section about the security freeze lock com m and describes locked mode and frozen m ode.) table 5.12 contents of securi ty passw ord word cont ent s 0 c ont rol word bit 0 : id en tifier 0 = com p ares t h e user passwords. 1 = com pares the master passwords. bits 1 to 15: reserved 1 to 16 password (32 bytes) 17 to 255 reserved
c141-e110-02en 5 - 63 at com m a nd issuance (i-o registers setting contents) 1f7 h (cm) 11110110 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at command completion (i-o registers setting contents) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (31) security erase prepare (f3h) the security erase unit com m a nd feature is enabled by issuing the security erase prepare com m a nd and t h en t h e security erase unit com m a nd. the security era s e prepa r e co m m an d p r ev en ts d ata fro m b ein g erased u n n ecessarily b y th e secu rity erase unit com m and. issuing th i s com m a nd duri ng frozen m ode ret u rns t h e abort e d com m and error.
c141-e110-02en 5 - 64 at com m a nd issuance (i-o registers setting contents) 1f7 h (cm) 11110011 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at command completion (i-o registers setting contents) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (32) security erase unit (f4h) this com m a nd erases all user data. this com m a nd also invalidates the user password and releases th e lo ck fu n c tio n . the host t r ansfers t h e 512-by t e dat a shown i n tabl e 1.1 t o t h e devi ce. the devi ce com p ares t h e user password or m a st er password i n t h e t r ansferred dat a wi t h t h e user password or m a st er password already set. the device erases user data, invalidates the user password, and releases the l o ck funct i on i f t h e passwords are t h e sam e . al t hough t h i s com m a nd i nval i d at es t h e user password, t h e m a st er password i s ret a i n ed. to recover t h e m a st er password, i ssue t h e security set password com m and and reset t h e user password. if t h e security erase prepare com m and i s not i ssued i m m e di at el y before t h i s com m and i s i ssued, t h e abort e d com m a nd error i s ret u rned. issui ng t h i s com m a nd whi l e i n frozen m ode ret u rns t h e abort e d com m and error.
c141-e110-02en 5 - 65 at com m a nd issuance (i-o registers setting contents) 1f7 h (cm) 11110100 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at command completion (i-o registers setting contents) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (33) security freeze lock (f5h) thi s com m a nd put s t h e devi ce i n t o frozen m ode. the fol l owi ng com m a nds used t o change t h e l o ck funct i on ret u rn t h e abort e d com m a nd error i f t h e devi ce i s i n frozen m ode. security set passw ord security unlock security disable passw ord security erase unit frozen m ode i s cancel ed when t h e power i s t u rned off. if t h i s com m a nd i s rei ssued i n frozen m ode, t h e com m a nd i s com p l e t e d and frozen m ode rem a i n s unchanged. issui ng t h i s com m a nd duri ng locked m ode ret u rns t h e abort e d c o m m a nd error. the following medium access commands return the aborted command error when the device is in locked mode:
c141-e110-02en 5 - 66 read dm a w r ite dma security disable passw ord read long w r ite long security freeze lock read multiple w r ite multiple security set passw ord read sectors w r ite sectors w r ite vetify at com m a nd issuance (i-o registers setting contents) 1f7 h (cm) 11110101 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at command completion (i-o registers setting contents) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (34) security set password (f1h) thi s com m a nd enabl e s a user password or m a st er password t o be set . the host t r ansfers t h e 512-by t e dat a shown i n tabl e 1.2 t o t h e devi ce. the devi ce det e rm i n es t h e operation of the lock function according to the specifications of the identifier bit and security lev el b it in th e tran sferred d ata. (tab le 1 . 3 ) issui ng t h i s com m a nd i n locked m ode or frozen m ode ret u rns t h e abort e d com m a nd error.
c141-e110-02en 5 - 67 tabl e 5.13 contents of security set password data word cont ent s 0 c ont rol word bit 0 id en tifier 0 = set s a user password. 1 = set s a m a st er password. bits 1 to 7 reserv ed bit 8 secu rity lev e l 0 = hi gh 1 = maximum bits 9 to 15 reserved 1 to 16 password (32 bytes) 17 to 255 reserved table 5.14 relationship between combination of identifier and security level, and operation of the lock function indentifier level description user hi gh the speci fi ed password i s saved as a new user password. the l o ck funct i on i s enabl e d aft e r t h e devi ce i s t u rned off and t h en on. locked mode can be canceled using the user password or the master password already set. master high the specified password is saved as a new master password. the lock function is not enabled. user m a xi m u m t he speci fi ed password i s saved as a new user password. the l o ck funct i on i s enabl e d aft e r t h e devi ce i s t u rned off and t h en on. locked mode can be canceled using the user password only. the master password already set cannot cancel locked mode. master maximum the specified password is saved as a new master password. the lock function is not enabled.
c141-e110-02en 5 - 68 at com m a nd issuance (i-o registers setting contents) 1f7 h (cm) 11110001 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at command completion (i-o registers setting contents) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (35) security unlock (f2h) this com m a nd cancels locked mode. the host t r ansfers t h e 512-by t e dat a shown i n tabl e 1.1 t o t h e devi ce. operat i on of t h e devi ce vari es as fol l ows dependi ng on whet h er t h e host speci fi es t h e m a st er password or user password. w h en the m a ster password is selected w h en th e secu rity lev e l in lo ck ed mo d e is h i g h , th e p a ssw o r d is co m p ared w ith th e m a ster password already set. if the passwords are the sam e , locked mode is canceled. otherwise, the aborted com m a nd error is returned. if the security level in locked mode i s set t o t h e hi ghest l e vel , t h e abort e d com m and error i s al way s ret u rned. w h en the user password is selected the password is com p ared with the user password already set. if the passwords are the sam e , locked m ode i s cancel ed. ot herwi s e, t h e abort e d com m and error i s ret u rned. if t h e password com p ari s on fai l s , t h e devi ce decrem ent s t h e unlock count er. the unlock counter initially has a value of five. w h en the value of the unlock counter reaches zero, this com m a nd or t h e security erase unit com m a nd causes t h e abort e d com m a nd error unt i l th e d ev i ce is tu rn ed o ff an d th en o n , o r u n til a h ard w are reset is ex ecu ted . issu in g th is co m m an d with locked m ode cancel ed (i n unlock m ode) has no affect on t h e unlock count er. issui ng t h i s com m a nd i n frozen m ode ret u rns t h e abort e d com m a nd error.
c141-e110-02en 5 - 69 at com m a nd issuance (i-o registers setting contents) 1f7 h (cm) 11110010 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx at command completion (i-o registers setting contents) 1f7 h (st) status information 1f6 h (dh) dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) xx xx xx xx error information (36-1) set m ax address (f9) this com m a nd allows the m a xim u m address accessible by the user to be set in lba or chs m ode. upon receipt of the com m a nd, the device sets the bsy bit and saves the m a xim u m address specified in the dh, ch, cl and sn registers. then, it clears bsy and generates an interrupt. the new address i n form at i on set by t h i s com m a nd i s refl ect ed i n words 1, 54, 57, 58, 60 and 61 of identify device i n form at i on. if an at t e m p t i s m a de t o perform a read or wri t e operat i o n for an address beyond the new address space, an id not found error will result. w h en sc reg i ster b it 0 , v v (v alu e v o l atile), is 1 , th e v alu e set b y th is co m m an d is h eld ev en after power on and t h e occurrence of a hard reset . when t h e vv bi t i s 0, t h e val u e set by t h i s com m a nd becom e s i nvali d when t h e power i s t u rned on, and t h e m a xi m u m address ret u rns t o t h e v alu e (d efau lt v alu e if n o t set) m o st lately set w h en v v b it = 1 . aft e r power on and t h e occurrence of a hard reset , t h e host can i ssue t h i s com m a nd onl y once when vv bi t = 1. if t h i s com m a nd wi t h vv bi t = 1 i s i ssued t w i ce or m o re, any com m and following the first tim e will result in an aborted com m a nd error.
c141-e110-02en 5 - 70 at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s ) 1f7 h (cm) 11111001 1f6 h (dh) l dv max head/lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) max. cylinder [msb]/max. lba max. cylinder [lsb]/max. lba max. sector/max. lba [lsb] 1f2 h (sc) xx vv 1f1 h (fr) xx at command completion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) dv max head/lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) max. cylinder [msb]/max. lba max. cylinder [lsb]/max. lba max. sector/max. lba [lsb] 1f2 h (sc) xx 1f1 h (er) error information (36-2) set m ax set password (f9) thi s com m and request s a t r ansfer of si ngl e sect or of dat a from t h e host , and defi nes t h e cont ent of this sector of inform ation. the password is retained by the device until the next power cycle. at command issuance (i/o registers setting contents) 1f7 h (cm) 11111001 1f6 h (dh) 1 l 1 dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) xx xx xx xx 1f1 h (fr) 00000001
c141-e110-02en 5 - 71 at com m and com p l e t i on (i/ o regi st ers cont ent s t o be read) 1f7 h (st) status information 1f6 h (dh) 1 l 1 dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) xx xx xx xx 1f1 h (fr) error information set m ax set password dat a cont ent word content 0 reserved 1 - 16 password (32 bytes) 17 - 255 reserved (36-3) set m ax lock (f9) aft e r t h i s com m a nd i s com p l e t e d any ot her set m a x com m ands except set m ax unlock and set max freeze lock are rejected. the device rem a ins in this state until a power cycle or the acceptance of a set max unlock or set max freeze lock com m a nd. at command issuance (i/o registers setting contents) 1f7 h (cm) 11111001 1f6 h (dh) 1 l 1 dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) xx xx xx xx 1f1 h (fr) 00000010 at command completion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) 1 l 1 dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) xx xx xx xx 1f1 h (fr) error information
c141-e110-02en 5 - 72 (36-4) set m ax unlock (f9) thi s com m a nd request s a t r ansfer of a si ngl e sect or of dat a from t h e host . the password suppl i e d i n t h e sect or of dat a t r ansferred shal l be com p ared wi t h t h e st ored set m ax password. if the password com p are fails, then the device returns com m a nd aborted and decrem ents the unlock counter. on the acceptance of the set max lock com m and, this counter is set to a value of five and shall be decrem ented for each password m i sm atch when set max unlock is issued and the device is locked. w h en this counter reaches zero, then the set max unlock com m and shall return com m a nd aborted until a power cycle. if the password com p are m a tches, then the device shall m a ke a transition to the set_max_unlocked state and all set max com m ands will be accepted. at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s) 1f7 h (cm) 11111001 1f6 h (dh) 1 l 1 dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) xx xx xx xx 1f1 h (fr) 00000011 at command completion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) 1 l 1 dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) xx xx xx xx 1f1 h (fr) error information (36-5) set max freeze lock (f9) this set max freeze lock com m a nd sets the device to set_max_frozen state. after com m a nd com p l e t i on any subsequent set m ax com m ands are reject ed. com m ands di sabled by set max freeze lock are:
c141-e110-02en 5 - 73 set m ax address set max set passw ord set max lock set m ax unlock at com m a nd i ssuance (i/ o regi st ers set t i ng cont ent s ) 1f7 h (cm) 11111001 1f6 h (dh) 1 l 1 dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) xx xx xx xx 1f1 h (fr) 00000100 at command completion (i/o registers contents to be read) 1f7 h (st) status information 1f6 h (dh) 1 l 1 dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) xx xx xx xx 1f1 h (fr) error information (37) read native m ax address (f8) thi s com m and post s t h e m a xi m u m address i n t r i n si c t o t h e devi ce, whi ch can be set by t h e set max address com m a nd. upon receipt of this com m and, the device sets the bsy bit and indicates the m a xim u m address in the dh, ch, cl and sn registers. then, it clears bsy and generat e s an i n t e rrupt . at command completion (i/o registers setting contents) 1f7 h (cm) 11111000 1f6 h (dh) l dv xx 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (fr) xx xx xx xx xx
c141-e110-02en 5 - 74 at com m a nd com p l e t i on (i/ o regi st ers cont ent s t o be read) 1f7 h (st) status information 1f6 h (dh) dv max head/lba [msb] 1f5 h (ch) 1f4 h (cl) 1f3 h (sn) 1f2 h (sc) 1f1 h (er) max. cylinder [msb]/max. lba max. cylinder [lsb]/max. lba max. sector/max. lba [lsb] xx error information
c141-e110-02en 5 - 75 5.3.3 e rror posting table 5.14 lists the defined errors that are valid for each com m a nd. table 5.15 command code and parameters com m a nd nam e error register (x' 1 f1' ) status register (x' 1 f7' ) icrc unc indf abrt tr0nf drdy dwf err read sector(s) v v v v v v write sector(s) v v v v v read multiple v v v v v v write multiple v v v v v read dma v v v v v v v write dma v v v v v v write verify v v v v v v read verify sector(s) v v v v v v recalibrate v v v v v seek v v v v v initialize device parameters v v v v identify device v v v v identify device dma v v v v set features v v v v set multiple mode v v v v execute device diagnostic * * * * * v format track v v v v v read long v v v v v write long v v v v v read buffer v v v v write buffer v v v v idle v v v v idle immediate v v v v standby v v v v standby immediate v v v v sleep v v v v check power mode v v v v smart v v v v v flush cache v v v v v security disable password v v v v security erase prepare v v v v security erase unit v v v v security freeze lock v v v v security set password v v v v security unlock v v v v set max address v v v v v read native max address v v v v invalid command v v v v v: valid on this com m a nd *: see the command descriptions.
c141-e110-02en 5 - 76 5.4 command protocol the host shoul d confi r m t h at t h e bsy bi t of t h e st at us regi st er of t h e devi ce i s 0 pri o r t o i ssue a com m a nd. if bsy bit is 1, the host should wait for issuing a com m and until bsy bit is cleared to 0. com m a nds can be execut e d onl y when t h e drdy bi t of t h e st at us regist er i s 1. however, t h e fol l owi ng com m ands can be execut e d even i f drdy bi t i s 0. execute device diagnostic initialize device parameters 5.4.1 data transferring commands from device to host the execut i on of t h e fol l owi ng com m ands i nvolves dat a t r ansfer from t h e devi ce t o t h e host . identify device identify device dm a read sector(s) read long read buffer sm art: sm art read at t r i but e val u es, sm art read at t r i but e threshol ds the execution of these com m a nds includes the transfer one or m o re sectors of data from the devi ce t o t h e host . in t h e read long com m a nd, 516 by t e s are t ransferred. fol l owi ng shows th e p r o t o c o l o u tlin e. a) the host wri t e s any requi red param e t e rs t o t h e feat ures, sect or count , sector num ber, cy l i nder, and devi ce/ head regi st ers. b) the host wri t e s a com m a nd code t o t h e com m a nd regi st er. c) the device sets the bsy bit of the status register and prepares for data transfer. d) when one sect or (or bl ock) of dat a i s avai l a bl e for t r ansfer t o t h e host , t h e devi ce set s drq bi t and clears bsy bit. the drive then asserts intrq signal. e) aft e r det ect i ng t h e intrq si gnal assert i on, t h e host reads t h e st at us regi st er. the host reads one sector of dat a vi a t h e dat a regi st er. in response t o t h e st at us regi st er bei ng read, t h e device negat e s th e intrq si gnal. f) the dri v e cl ears drq bi t t o 0. if t r ansfer of anot her sect or i s request ed, t h e devi ce set s t h e bsy bit and steps d) and after are repeated. even if an error is encountered, the device prepares for data transfer by setting the drq bit. w h ether or not to transfer the data is determ ined for each host. in other words, the host should receive the relevant sector of data (512 bytes of uninsured dum m y data) or release the drq status by reset t i ng. fi gure 5.2 shows an exam pl e of read sector(s) com m and prot ocol , and fi gure 5.3 shows an exam pl e prot ocol for com m a nd abort .
c141-e110-02en 5 - 77 s tatu s r e ad s tatu s r e ad * 1 wh en t h e i d d r ecei v es a co mman d th at h its th e c ac h e d ata d u r in g r e ad - ah e ad , an d tr an s f e r s d ata f r o m th e b u f f e r w ith o u t r e ad in g f r o m th e d i s k me d i u m . 255 2 1 0 wo r d io cs 16- io r - d ata d ata r e g . s e le c tio n in t r q dr q m i n . 30 m s (*1) e xpa n de d c o mman d fd d e e c b a c o mman d bs y in t r q dr dy ~ p ar ame te r w r ite dr q d ata tr ansfer ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 5.2 r ead sector(s) command protocol even if the error status exists, the drive m a kes a preparation (setting the drq bit) of data transfer. it is up to the host whether data is transferred. in other words, the host should receive the data of the sector (512 bytes of uninsured dum m y data) or release the drq by resetting.
c141-e110-02en 5 - 78 note: for transfer of a sector of data, the host needs to read status register (x'1f7') in order to clear intrq (i nt errupt ) si gnal. the st at us regi st er shoul d be read wi t h i n a peri od from t h e drq set t i ng by t h e devi ce t o st art i ng of t h e sect or dat a t r ansfer. not e t h at t h e host does not need t o read th e statu s reg i ster fo r th e read in g o f a sin g l e secto r o r th e last secto r in m u ltiple-secto r reading. if the tim ing to read the status register does not m eet above condition, norm a l data t ransfer operat i on i s not guarant eed. when t h e host new com m a nd even i f t h e devi ce request s t h e dat a t r ansfer (sett i ng i n drq bi t ), t h e correct devi ce operat i on i s not guarant eed. * tr an s f e r s d ummy d ata * t h e h o s t s h o ul d r ecei v e 512-by t e dummy data o r r e le as e th e d r q s e t s tate b y r e s e ttin g. s tatu s r e ad co mman d bs y in t r q dr dy ~ p ar ame te r w r ite dr q data tran s f e r figure 5.3 p rotocol for command abort 5.4.2 data transferring commands from host to device the execut i on of t h e fol l owi ng com m ands i nvol ves dat a t r ansfer from t h e host t o t h e dri v e. form at track w r ite sector(s) w r ite long w r ite buffer w r ite verify security disable passw ord security erase unit security set passw ord security unlock the execution of these com m a nds includes the transfer one or m o re sectors of data from the host t o t h e devi ce. in t h e write long com m a nd, 516 by t e s are t ransferred. fol l owi ng shows t h e p r o t o c o l o u tlin e.
c141-e110-02en 5 - 79 a) the host wri t e s any requi red param e t e rs t o t h e feat ures, sect or count , sect or num ber, cy l i nder, and devi ce/ head regi st ers. b) the host wri t e s a com m a nd code i n t h e com m and regi st er. the dri v e set s t h e bsy bi t of t h e st at us regi st er. c) w h en the device is ready to receive the data of the first sector, the device sets drq bit and clears bsy bit. d) the host wri t e s one sect or of dat a t h rough t h e dat a regi st er. e) the device clears the drq bit and sets the bsy bit. f) w h en the drive com p letes transferring the data of the sector, the device clears bsy bit and assert s intrq si gnal. if t r ansfer of anot her sect or i s request ed, t h e dri v e set s t h e drq bi t . g) aft e r det ect i ng th e intrq si gnal assert i on, t h e host reads t h e stat us regi st er. h) the devi ce reset s intrq (t he i n t e rrupt signal) . i) if transfer of another sector is requested, steps d) and after are repeated. fi gure 5.4 shows an exam pl e of write sector(s) com m and prot ocol , and fi gure 5.3 shows an exam pl e prot ocol for com m a nd abort . s t atus r e ad s t atus r e ad 255 2 1 0 wo r d io cs 1 6 io r - da t a d a ta r e g. s e le c tio n dr q ma x. 1 m s ex pan d e d c o mman d e c dd h g g f b a c o mman d bs y in t r q dr dy ~ p a r a me te r w r ite dr q data transfer ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 5.4 write sector(s) command protocol
c141-e110-02en 5 - 80 note: for transfer of a sector of data, the host needs to read status register (x'1f7') in order to clear intrq (i nt errupt ) si gnal. the st at us regi st er shoul d be read wi t h i n a peri od from t h e drq set t i ng by t h e devi ce t o st art i ng of t h e sect or dat a t r ansfer. not e t h at t h e host does not need t o read the status register for the first and the last sector to be transferred. if the tim ing to read the status register does not m eet above condition, norm a l data transfer operation is not assured guarant eed. w h en the host issues the com m a nd even if the drive requests the data transfer (drq bit is set ), or when t h e host execut e s reset t i ng, t h e devi ce correct operat i on i s not guarant eed. 5.4.3 commands without data transfer execut i on of t h e fol l owi ng com m a nds does not i nvol ve dat a t ransfer bet w een t h e host and t h e device. recalibrate seek ready verify sector(s) execute device diagnostic initialize device parameters set features set multiple mode idle idle im m ediate standby standby im m ediate check power m ode flush cache security erase prepare security freeze lock sm art: except for sm art read at t r i but e val u es and sm art read at t r i but e threshol ds set m ax address read native m ax address fi gure 5.5 shows t h e prot ocol for t h e com m a nd execut i on wi t hout dat a t ransfer. s tatu s r e ad co mman d bs y in t r q dr dy ~ p ar ame te r w r ite figure 5.5 p rotocol for the command execution without data transfer
c141-e110-02en 5 - 81 5.4.4 o ther commands read multiple sleep w r ite multiple see the description of each com m a nd. 5.4.5 d ma data transfer commands read dm a w r ite dma st art i ng t h e dm a t r ansfer com m a nd i s t h e sam e as t h e read sector(s) or write sector(s) com m a nd except the point that the host initializes the dma channel preceding the com m a nd issuance. the i n t e rrupt processi ng for t h e dm a transfer di ffers t h e fol l owi ng poi nt . the i n t e rrupt processi ng for t h e dm a transfer di ffers t h e fol l owi ng poi nt . a) the host writes any param e ters to the features, sector count, sector num ber, cylinder, and devi ce/ head regi st er. b ) th e h o st in itializes th e d m a ch an n e l c) the host wri t e s a com m a nd code i n t h e com m and regi st er. d) the devi ce set s t h e bsy bi t of t h e st at us regi st er. e) the devi ce assert s t h e dm arq si gnal aft e r com p l e t i ng t h e preparat i on of dat a t r ansfer. the devi ce assert s ei t h er t h e bsy bi t duri ng dm a dat a t r ansfer. f) when t h e com m a nd execut i on i s com p l e t e d, t h e devi ce cl ears bot h bsy and drq bi t s and asserts the intrq signal. g) the host reads the status register. h) the host reset s t h e dm a channel .
c141-e110-02en 5 - 82 s tatu s r e ad e xpa n de d g f e c, d a c o mman d bs y i ntrq dr dy ~ p ar ame te r w r ite dr q d ata transfer ? ? ? ? dr q [m u ltiw o r d dma t r a n sf e r ] ? ? ? ? dmac k- dmarq ? ? ? ? i o r- or io w - ? ? ? ? ? ? ? ? 01 w o rd n- 1 n ? ? fi gure 5.6 normal dma data transfer
c141-e110-02en 5 - 83 5.5 u l t ra dma feature set 5.5.1 overvi e w ul t ra dm a i s a dat a t ransfer prot ocol used wi t h t h e read dm a and write dm a com m a nds. when t h i s prot ocol i s enabl e d i t shal l be used i n st ead of t h e m u l t i word dm a prot ocol when t h ese com m a nds are i ssued by t h e host . thi s prot ocol appl i e s t o t h e ul t r a dm a dat a burst onl y . when t h i s prot ocol i s used t h ere are no changes t o ot her el em ent s of t h e ata protocol (e.g.: com m a nd block register access). several si gnal l i n es are redefi ned t o provi de new funct i ons duri ng an ul t r a dm a burst . these l i n es assum e t h ese defi ni t i ons when 1) an ul t r a dm a m ode i s sel ect ed, and 2) a host i ssues a read dm a or a write dm a, com m a nd requi ri ng dat a t ransfer, and 3) t h e host assert s dm ack-. these si gnal l i n es revert back t o t h e defi ni t i ons used for non-ul t r a dm a t r ansfers upon t h e negat i on of dm ack- by t h e host at t h e t e rm i n at i on of an ul t ra dm a burst . al l of t h e cont rol si gnal s are uni di rect i onal . dm arq and dm ack- ret a i n t h ei r st andard defi ni t i ons. wi t h t h e ul t ra dm a prot ocol , t h e cont rol si gnal (strobe) t h at l a t c hes dat a from dd (15: 0) i s generat e d by t h e sam e agent (ei t h er host or device) t h at dri v es t h e dat a ont o t h e bus. ownershi p of dd (15: 0) and t h i s dat a st robe si gnal are gi ven ei t h er t o t h e devi ce duri ng an ul t ra dm a dat a i n burst or t o t h e host for an ul t ra dm a dat a out burst . during an ul t r a dm a burst a sender shal l al way s dri v e dat a ont o t h e bus, and aft e r a suffi ci ent tim e to allo w fo r p r o p ag ation d elay, cab le settlin g , an d setu p tim e, th e sen d er sh all g en erate a strobe ed g e to latch th e d ata. bo th ed g es o f stro be are u sed fo r d ata transfers so th at th e frequency of strobe i s l i m i t e d t o t h e sam e frequency as t h e dat a . the hi ghest fundam e nt al frequency on the cable shall be 16.67 m illion transitions per second or 8.33 mhz (the sam e as the m a xi m u m frequency for pio m ode 4 and dm a m ode 2). words i n t h e identify device dat a i ndi cat e support of t h e ul t r a dm a feat ure and t h e ul t r a dm a m odes t h e devi ce i s capabl e of support i ng. the set t r ansfer m ode subcom m a nd i n t h e set features com m a nd shal l be used by a host t o sel ect t h e ul t r a dm a m ode at whi ch t h e sy st em operat e s. the ul t r a dm a m ode sel ect ed by a host shal l be l e ss t h an or equal t o t h e fastest m ode of which the device is capable. only the ultra dma mode shall be selected at any given tim e. al l t i m i ng requi rem e nt s for a sel ect ed ul t r a dm a m ode shal l be sat i sfi ed. devi ces support i n g ul t ra dm a m ode 2 shal l al so support ul t ra dm a m odes 0 and 1. devi ces support i ng ul t ra dm a m ode 1 shal l al so support ul t ra dm a m ode 0. a n u ltra d m a cap ab le d ev i ce sh all retain its p r ev io u sly selected u ltra d m a mo d e after executing a software reset sequence. an ultra dma capable device shall clear any previously sel ect ed ul t r a dm a m ode and revert t o i t s defaul t non-ul t r a dm a m odes aft e r execut i ng a power on or hardware reset . both the host and device perform a crc function during an ultra dma burst. at the end of an ultra dma burst the host sends the its crc data to the device. the device com p ares its crc dat a t o t h e dat a sent from t h e host . if t h e t wo val u es do not m a t c h t h e devi ce report s an error i n t h e error regi st er at t h e end of t h e com m and. if an error occurs during one or m o re ul t r a dm a bursts for any one com m a nd, at the end of the com m and, the device shall report the first error that occurred.
c141-e110-02en 5 - 84 5.5.2 p hases of operati on an ultra dma data transfer is accom p lished through a series of ultra dma data in or data out b u r sts. each u ltra d m a b u r st h as th ree m an d ato ry p h ases o f o p eratio n: th e in itiatio n p h ase, th e dat a t ransfer phase, and t h e ul t ra dm a burst t e rm i n at i on phase. in addi t i on, an ul t ra dm a burst m a y be paused duri ng t h e dat a t ransfer phase (see 5.5.3 and 5.5.4 for t h e det a i l e d prot ocol descriptions for each of these phases, 5.6 defines the specific tim ing requirem e nts). in the fol l owi ng rul e s dm ardy- i s used i n cases t h at coul d appl y t o ei t h er ddm ardy- or hdm ardy-, and strobe i s used i n cases t h at coul d appl y t o ei t h er dstrobe or hstrobe. the fol l owi ng are general ult r a dm a rul e s. a) an ul t ra dm a burst i s defi ned as t h e peri od from an assert i on of dm ack- by t h e host t o t h e subsequent negat i on of dm ack-. b) a recipient shall be prepared to receive at least two data words whenever it enters or resum e s an ul t ra dm a burst . 5.5.3 u l tra dma data i n commands 5.5.3.1 ini ti ati n g an ul tra dma data i n burst th e fo llo w i n g step s sh all o ccu r in th e o r d er th ey are listed u n l ess o t h erw ise sp ecifically allow ed (see 5.6.3.1 and 5.6.3.2 for speci fi c t i m i ng requi rem e nt s): 1 ) th e h o st sh all k eep d m a c k - in th e n eg ated state b efo re an u ltra d m a b u r st is in itiated . 2 ) th e d ev i ce sh all assert d m a r q to in itiate an u ltra d m a b u r st. a f ter assertio n o f d m a r q th e d ev i ce sh all n o t n eg ate d m a r q u n til after th e first n eg ation o f d s tro b e. 3) steps (3), (4) and (5) m a y occur in any order or at the sam e tim e. the host shall assert stop. 4) the host shal l negat e hdm ardy-. 5) the host shall negat e cs0-, cs1-, da2, da1, and da0. the host shal l keep cs0-, cs1-, da2, da1, and da0 negated until after negating dmack- at the end of the burst. 6) steps (3), (4) and (5) shall have occurred at least t ack before t h e host assert s dm ack-. the h o st sh all k eep d m a c k - asserted u n til th e en d o f an u ltra d m a b u r st. 7) the host shal l release dd (15: 0) wi t h i n t az aft e r assert i ng dm ack-. 8) the devi ce m a y assert dstrobe t ziordy aft e r t h e host has assert ed dm ack-. once t h e d ev i ce h as d r iv en d s tro b e th e d ev i ce sh all n o t release d s tro b e u n til after th e h o st h as negat e d dm ack- at t h e end of an ul t ra dm a burst . 9) the host shal l negat e stop and assert hdm ardy- wi t h i n t env aft e r assert i ng dm ack-. aft e r negat i ng stop and assert i ng hdm ardy-, t h e host shal l not change t h e st at e of ei t h er signal until after receiving the first transition of dstrobe from the device (i.e., after the first data word has been received). 10) the devi ce shal l dri v e dd (15: 0) no sooner t h an t zad aft e r t h e host has assert ed dm ack-, negat e d stop, and assert ed hdm ardy-.
c141-e110-02en 5 - 85 11) the devi ce shal l dri v e t h e fi rst word of t h e dat a t r ansfer ont o dd (15: 0). thi s st ep m a y occur when t h e devi ce fi rst dri v es dd (15: 0) i n st ep (10). 12) to t r ansfer t h e fi rst word of dat a t h e devi ce shal l negat e dstrobe wi t h i n t fs after th e h o st has negat e d stop and assert ed hdm ardy-. the devi ce shal l negat e dstrobe no sooner th an t dvs aft e r dri v i ng t h e fi rst word of dat a ont o dd (15: 0). 5.5.3.2 t he data i n transfer th e fo llo w i n g step s sh all o ccu r in th e o r d er th ey are listed u n l ess o t h erw ise sp ecifically allow ed (see 5.6.3.3 and 5.6.3.2 for speci fi c t i m i ng requi rem e nt s): 1) the devi ce shal l dri v e a dat a word ont o dd (15: 0). 2) the devi ce shal l generat e a dstrobe edge t o l a t c h t h e new word no sooner t h an t dvs after changi ng t h e st at e of dd (15: 0). the devi ce shall generat e a dstrobe edge m o re freq u e n tly th an t cyc for t h e sel ect ed ul t r a dm a m ode. the devi ce shal l not generat e t w o risin g o r tw o fallin g d s tro b e ed g es m o re freq u en tly th an 2 t cyc for the selected ultra dma m ode. 3 ) th e d e v i ce sh all n o t ch an g e th e state o f d d (1 5 : 0 ) u n til at least t dvh aft e r generat i ng a dstrobe edge t o l a t c h th e dat a . 4 ) th e d ev i ce sh all rep eat steps (1 ), (2 ) an d (3 ) u n til th e d ata tran sfer is co m p lete o r an u ltra dm a burst i s paused, whi chever occurs fi rst . 5.5.3.3 pausi ng an ul tra dma data i n burst th e fo llo w i n g step s sh all o ccu r in th e o r d e r th ey are listed u n l ess o t h erw ise sp ecifically allow ed (see 5.6.3.4 and 5.6.3.2 for speci fi c t i m i ng requi rem e nt s). a) device pausi ng an ul t r a dm a dat a i n burst 1 ) th e d e v i ce sh all n o t p a u se an u ltra d m a b u r st u n til at least o n e d a ta w o r d o f an u ltra dm a burst has been t r ansferred. 2) the devi ce shal l pause an ul t r a dma burst by not generat i ng dstrobe edges. n o te - th e h o st sh all n o t im m ed i ately assert sto p to in itiate u ltra d m a b u r st t e rm i n at i on when t h e devi ce st ops generat i ng strobe edges. if t h e devi ce does not n eg ate d m a r q , in o r d er to in itiate u ltra d m a b u r st term in ation, th e h o st sh all negat e hdm ardy- and wai t t rp before asserting stop. 3) the devi ce shal l resum e an ul t r a dm a burst by generat i ng a dstrobe edge. b) host pausi ng an ul t ra dm a dat a i n burst 1 ) th e h o st sh all n o t p a u se an u ltra d m a b u r st u n til at least o n e d a ta w o r d o f an u ltra dm a burst has been t r ansferred. 2) the host shal l pause an ul t ra dm a burst by negat i ng hdm ardy-.
c141-e110-02en 5 - 86 3) the devi ce shal l st op generat i ng dstrobe edges wi t h i n t rfs of t h e host negat i n g hdm ardy-. 4) if t h e host negat e s hdm ardy- wi t h i n t sr aft e r t h e devi ce has generat e d a dstrobe edge, then the host shall be prepared to receive zero or one additional data words. if the host negat e s hdm ardy- great er t h an t sr aft e r t h e devi ce has generat e d a dstrobe edge, then the host shall be prepared to receive zero, one or two additional data words. the addit i onal dat a words are a resul t of cabl e round t r i p del a y and t rfs tim in g fo r th e device. 5) the host shal l resum e an ul t ra dm a burst by assert i ng hdm ardy-. 5.5.3.4 t erminating an ultra dma data in burst a) device t e rm i n at i ng an ul t r a dm a dat a i n burst the following steps shall occur in the order they are listed unless otherwise specifically al l owed (see 5.6.3.5 and 5.6.3.2 for speci fi c t i m i ng requi rem e nt s): 1 ) th e d e v i ce sh all in itiate term in atio n o f an u ltra d m a b u r st b y n o t g e n e ratin g dstrobe edges. 2) the devi ce shal l negat e dm arq no sooner t h an t ss aft e r generat i ng t h e l a st dstrobe ed g e. th e d ev i ce sh all n o t assert d m a r q ag ain u n til after th e u ltra d m a b u r st is term in ated. 3) the devi ce shal l release dd (15: 0) no l a t e r t h an t az aft e r negat i ng dm arq. 4 ) th e h o st sh all assert sto p w ith in t li aft e r t h e device has negat e d dm arq. the host sh all n o t n eg ate stop ag ain u n til after th e u ltra d m a b u r st is term in ated. 5) the host shal l negat e hdm ardy- wi t h i n t li aft e r t h e devi ce has negat e d dm arq. the h o st sh all co n tin u e to n e g a te h d m a rd y - u n til th e u ltra d m a b u r st is term in ated . steps (4) and (5) m a y occur at the sam e tim e. 6) the host shal l dri v e dd (15: 0) no sooner t h an t zah aft e r t h e devi ce has negat e d d m a r q . fo r th is step, th e h o st m ay first d r iv e d d (1 5 : 0 ) w ith th e resu lt o f its crc cal cul a t i on (see 5.5.5): 7) if dstrobe i s negat e d, t h e devi ce shal l assert dstrobe wi t h i n t li after th e h o st h as assert ed stop. no dat a shal l be t r ansferred duri ng t h i s assert i on. the host shal l i gnore th is transitio n o n d s tro b e. d s tro b e sh all rem ain asserted u n til th e u ltra d m a b u r st is term in ated. 8) if the host has not placed the result of its crc calculation on dd (15:0) since first driving dd (15:0) during (6), the host shall place the result of its crc calculation on dd (15: 0) (see 5.5.5). 9) the host shal l negat e dm ack- no sooner t h an t mli after the device has asserted dstrobe and negat e d dm arq and t h e host has assert ed stop and negat e d hdm ardy-, and no sooner t h an t dvs after the host places the result of its crc cal cul a t i on on dd (15: 0).
c141-e110-02en 5 - 87 10) the device shall latch the host's crc data from dd (15:0) on the negating edge of dm ack-. 11) the device shall com p are the crc data received from the host with the results of its own crc calculation. if a m i scom pare error occurs during one or m o re ultra dma bursts for any one com m a nd, at the end of the com m a nd the device shall report the first error that occurred (see 5.5.5). 12) the devi ce shal l release dstrobe wi t h i n t iordyz aft e r th e host negat e s dm ack-. 1 3 ) th e h o st sh all n o t n e g a te sto p n o assert h d m a rd y - u n til at least t ack after n eg ating dm ack-. 14) the host shall not assert dior-, cs0-, cs1-, da2, da1, or da0 until at least t ack after negat i ng dm ack. b) host t e rm i n at i ng an ul t ra dm a dat a i n burst the following steps shall occur in the order they are listed unless otherwise specifically al l owed (see 5.6.3.6 and 5.6.3.2 for speci fi c t i m i ng requi rem e nt s): 1 ) th e h o st sh all n o t in itiate u ltra d m a b u r st term in atio n u n til at least o n e d a ta w o r d o f an ul t r a dm a burst has been t r ansferred. 2 ) th e h o st sh all in itiate u ltra d m a b u r st term in ation b y n eg ating h d m a r d y -. th e h o st sh all co n tin u e to n eg ate h d m a r d y - u n til th e u ltra d m a b u r st is term in ated. 3) the devi ce shal l st op generat i ng dstrobe edges wi t h i n t rfs of t h e host negat i n g hdm ardy-. 4) if t h e host negat e s hdm ardy- wi t h i n t sr aft e r t h e devi ce has generat e d a dstrobe edge, then the host shall be prepared to receive zero or one additional data words. if the host negat e s hdm ardy- great er t h an t sr aft e r t h e devi ce has generat e d a dstrobe edge, then the host shall be prepared to receive zero, one or two additional data words. the addit i onal dat a words are a resul t of cabl e round t r i p del a y and t rfs tim in g fo r th e device. 5) the host shall assert stop no sooner t h an t rp aft e r negat i ng hdm ardy-. the host sh all n o t n eg ate stop ag ain u n til after th e u ltra d m a b u r st is term in ated. 6) the device shal l negat e dm arq wi t h i n t li aft e r t h e host has assert ed stop. the devi ce sh all n o t assert d m a r q ag ain u n til after th e u ltra d m a b u r st is term in ated. 7) if dstrobe i s negat e d, t h e devi ce shal l assert dstrobe wi t h i n t li after th e h o st h as assert ed stop. no dat a shal l be t r ansferred duri ng t h i s assert i on. the host shal l i gnore th is transitio n o n d s tro b e. d s tro b e sh all rem ain asserted u n til th e u ltra d m a b u r st is term in ated. 8) the devi ce shal l release dd (15: 0) no l a t e r t h an t az aft e r negat i ng dm arq. 9) the host shal l dri v e dd (15: 0) no sooner t h an t zah aft e r t h e devi ce has negat e d d m a r q . fo r th is step, th e h o st m ay first d r iv e d d (1 5 : 0 ) w ith th e resu lt o f its crc cal cul a t i on (see 5.5.5).
c141-e110-02en 5 - 88 10) if the host has not placed the result of its crc calculation on dd (15:0) since first driving dd (15:0) during (9), the host shall place the result of its crc calculation on dd (15: 0) (see 5.5.5). 11) the host shal l negat e dm ack- no sooner t h an t mli after the device has asserted dstrobe and negat e d dm arq and t h e host has assert ed stop and negat e d hdm ardy-, and no sooner t h an t dvs after the host places the result of its crc cal cul a t i on on dd (15: 0). 12) the device shall latch the host's crc data from dd (15:0) on the negating edge of dm ack-. 13) the device shall com p are the crc data received from the host with the results of its own crc calculation. if a m i scom pare error occurs during one or m o re ultra dma burst for any one com m a nd, at the end of the com m a nd, the device shall report the first error that occurred (see 5.5.5). 14) the devi ce shal l release dstrobe wi t h i n t iordyz aft e r th e host negat e s dm ack-. 1 5 ) th e h o st sh all n e ith er n e g a te sto p n o r assert h d m a rd y - u n til at least t ack after th e host has negat e d dm ack-. 16) the host shal l not assert dior-, cs0-, cs1-, da2, da1, or da0 unt i l at l east t ack after negat i ng dm ack. 5.5.4 u l tra dma data out commands 5.5.4.1 ini ti ati n g an ul tra dma data out burst th e fo llo w i n g step s sh all o ccu r in th e o r d er th ey are listed u n l ess o t h erw ise sp ecifically allow ed (see 5.6.3.7 and 5.6.3.2 for speci fi c t i m i ng requi rem e nt s): 1 ) th e h o st sh all k eep d m a c k - in th e n eg ated state b efo re an u ltra d m a b u r st is in itiated . 2 ) th e d ev i ce sh all assert d m a r q to in itiate an u ltra d m a b u r st. 3) steps (3), (4), and (5) m a y occur in any order or at the sam e tim e. the host shall assert stop. 4) the host shall assert hstrobe. 5) the host shall negat e cs0-, cs1-, da2, da1, and da0. the host shal l keep cs0-, cs1-, da2, da1, and da0 negated until after negating dmack- at the end of the burst. 6) steps (3), (4), and (5) shall have occurred at least t ack before t h e host assert s dm ack-. the h o st sh all k eep d m a c k - asserted u n til th e en d o f an u ltra d m a b u r st. 7) the devi ce m a y negat e ddm ardy- t ziordy aft e r t h e host has assert ed dm ack-. once t h e d ev i ce h as n eg ated d d m a r d y -, th e d ev i ce sh all n o t release d d m a r d y - u n til after th e h o st has negat e d dm ack- at t h e end of an ul t r a dm a burst . 8) the host shal l negat e stop wi t h i n t env aft e r assert i ng dm ack-. the host shall not assert sto p u n til after th e first n eg ation o f h s tro b e.
c141-e110-02en 5 - 89 9) the devi ce shal l assert ddm ardy- wi t h i n t li aft e r t h e host has negat e d stop. aft e r assertin g d m a r q an d d d m a r d y - th e d ev i ce sh all n o t n eg ate eith er sig n al u n til after th e fi rst negat i on of hstrobe by t h e host . 10) the host shal l dri v e t h e fi rst word of t h e dat a t ransfer ont o dd (15: 0). thi s st ep m a y occur an y tim e d u r in g u ltra d m a b u r st in itiatio n . 11) to t r ansfer t h e fi rst word of dat a : t h e host shall negat e hstrobe no sooner t h an t li after th e device has assert ed ddm ardy-. the host shal l negat e hstrobe no sooner t h an t dvs after t h e dri v i ng t h e fi rst word of dat a ont o dd (15: 0). 5.5.4.2 t he data out transfer th e fo llo w i n g step s sh all o ccu r in th e o r d er th ey are listed u n l ess o t h erw ise sp ecifically allow ed (see 5.6.3.8 and 5.6.3.2 for speci fi c t i m i ng requi rem e nt s): 1) the host shal l dri v e a dat a word ont o dd (15: 0). 2) the host shal l generat e an hstrobe edge t o l a t c h t h e new word no sooner t h an t dvs after changi ng t h e st at e of dd (15: 0). the host shal l generat e an hstrobe edge m o re frequent l y th an t cyc fo r th e selected u ltra d m a mo d e. th e h o st sh all n o t g en erate tw o risin g o r fallin g h s tro b e ed g es m o re freq u en tly than 2 t cyc for the selected ultra dma m ode. 3 ) th e h o st sh all n o t ch an g e th e state o f d d (1 5 : 0 ) u n til at least t dvh aft e r generat i ng an hstrobe edge t o l a t c h th e dat a . 4 ) th e h o st sh all rep eat step s (1 ), (2 ) an d (3 ) u n til th e d ata transfer is co m p lete o r an u ltra d m a burst is paused, whichever occurs first. 5.5.4.3 pausi ng an ul tra dma data out burst th e fo llo w i n g step s sh all o ccu r in th e o r d er they are listed u n l ess o t h erw ise sp ecifically allow ed (see 5.6.3.9 and 5.6.3.2 for speci fi c t i m i ng requi rem e nt s). a) host pausi ng an ul t ra dm a dat a out burst 1 ) th e h o st sh all n o t p a u se an u ltra d m a b u r st u n til at least o n e d a ta w o r d o f an u ltra dm a burst has been t r ansferred. 2) the host shal l pause an ul t r a dma burst by not generat i ng an hstrobe edge. n o t e: th e d e v i ce sh all n o t im m e d i ately n e g a te d m a rq to in itiate u ltra d m a b u r st t e rm i n at i on when t h e host st ops generat i ng hstrobe edges. if t h e host does not assert sto p , in o r d er to in itiate u ltra d m a b u r st term in ation, th e d ev i ce sh all n eg ate ddm ardy- and wai t t rp before negat i ng dm arq. 3) the host shal l resum e an ul t r a dm a burst by generat i ng an hstrobe edge.
c141-e110-02en 5 - 90 b) devi ce pausi ng an ul t ra dm a dat a out burst 1 ) th e d e v i ce sh all n o t p a u se an u ltra d m a b u r st u n til at least o n e d a ta w o r d o f an u ltra dm a burst has been t r ansferred. 2) the devi ce shal l pause an ul t r a dma burst by negat i ng ddm ardy-. 3) the host shal l st op generat i ng hstrobe edges wi t h i n t rfs of t h e device negat i n g ddm ardy-. 4) if t h e devi ce negat e s ddm ardy- wi t h i n t sr aft e r t h e host has generat e d an hstrobe edge, then the device shall be prepared to receive zero or one additional data words. if t h e devi ce negat e s ddm ardy- great er t h an t sr aft e r t h e host has generat e d an hstrobe edge, then the device shall be prepared to receive zero, one or two additional dat a words. the addi t i onal dat a words are a resul t of cable round t r i p del a y and t rfs tim in g fo r th e h o st. 5) the devi ce shal l resum e an ul t r a dm a burst by assert i ng ddm ardy-. 5.5.4.4 t erminating an ultra dma data out burst a) host t e rm i n at i ng an ul t ra dm a dat a out burst the fol l owi ng st ops shal l occur i n t h e order t h ey are l i st e d unl ess ot herwi se speci fi cal l y al l owed (see 5.6.3.10 and 5.6.3.2 for speci fi c t i m i ng requi rem e nt s): 1 ) th e h o st sh all in itiate term in atio n o f an u ltra d m a b u r st b y n o t g e n e ratin g h s tro be edges. 2) the host shall assert stop no sooner t h an t ss aft e r i t l a st generat e d an hstrobe edge. th e h o st sh all n o t n eg ate stop ag ain u n til after th e u ltra d m a b u r st is term in ated. 3) the devi ce shal l negat e dm arq wi t h i n t li after the host asserts stop. the device shall n o t assert d m a r q ag ain u n til after th e u ltra d m a b u r st is term in ated. 4) the devi ce shal l negat e ddm ardy- wi t h t li aft e r t h e host has negat e d stop. the d ev i ce sh all n o t assert d d m a r d y - ag ain u n til after th e u ltra d m a b u r st term in ation is co m p lete. 5) if hstrobe i s negat e d, t h e host shal l assert hstrobe wi t h t li after the device has negat e d dm arq. no dat a shal l be t r ansferred duri ng t h i s assert i on. the devi ce shal l ignore this transition on hstrobe. hstrobe shall rem a in asserted until the ultra dm a burst i s t e rm i n at ed. 6) the host shall place the result of its crc calculation on dd (15:0) (see 5.5.5) 7) the host shal l negat e dm ack- no sooner t h an t mli after the host has asserted hstrobe and stop and t h e devi ce has negat e d dm arq and ddm ardy-, and no sooner t h an t dvs after placing the result of its crc calculation on dd (15:0). 8) the device shall latch the host's crc data from dd (15:0) on the negating edge of dm ack-.
c141-e110-02en 5 - 91 9) the device shall com p are the crc data received from the host with the results of its own crc calculation. if a m i scom pare error occurs during one or m o re ultra dma bursts for any one com m a nd, at the end of the com m a nd, the device shall report the first error that occurred (see 5.5.5). 10) the devi ce shal l rel ease ddm ardy- wi t h i n t iordyz aft e r t h e host has negat e d dm ack-. 1 1 ) th e h o st sh all n e ith er n e g a te sto p n o r n e g a te h s tro be u n til at least t ack after negat i ng dm ack-. 12) the host shall not assert diow -, cs0-, cs1-, da2, da1, or da0 until at least t ack after negat i ng dm ack. b) devi ce t e rm i n at i ng an ul t ra dm a dat a out burst th e fo llo w i n g step s sh all o ccu r in th e o r d er th ey are listed u n l ess o t h erw ise sp ecifically al l owed (see 5.6.3.11 and 5.6.3.2 for speci fi c t i m i ng requi rem e nt s): 1 ) th e d e v i ce sh all n o t in itiate u ltra d m a b u r st term in atio n u n til at least o n e d a ta w o r d o f an ul t r a dm a burst has been t r ansferred. 2 ) th e d ev i ce sh all in itiate u ltra d m a b u r st term in ation b y n eg ating d d m a r d y - . 3) the host shall st op generat i ng an hstrobe edges wi t h i n t rfs of t h e devi ce negat i n g ddm ardy-. 4) if t h e devi ce negat e s ddm ardy- wi t h i n t sr aft e r t h e host has generat e d an hstrobe edge, then the device shall be prepared to receive zero or one additional data words. if t h e devi ce negat e s ddm ardy- great er t h an t sr aft e r t h e host has generat e d an hstrobe edge, then the device shall be prepared to receive zero, one or two additional dat a words. the addi t i onal dat a words are a resul t of cable round t r i p del a y and t rfs tim in g fo r th e h o st. 5) the devi ce shal l negat e dm arq no sooner t h an t rp aft e r negat i ng ddm ardy-. the d ev i ce sh all n o t assert d m a r q ag ain u n til after th e u ltra d m a b u r st is term in ated. 6) the host shal l assert stop wi t h t li aft e r t h e devi ce has negat e d dm arq. the host shall n o t n eg ate stop ag ain u n til after th e u ltra d m a b u r st is term in ated. 7) if hstrobe i s negat e d, t h e host shal l assert hstrobe wi t h t li after the device has negat e d dm arq. no dat a shal l be t r ansferred duri ng t h i s assert i on. the devi ce shal l ignore this transition of hstrobe. hstrobe shall rem a in asserted until the ultra dm a burst i s t e rm i n at ed. 8) the host shall place the result of its crc calculation on dd (15:0) (see 5.5.5). 9) the host shal l negat e dm ack- no sooner t h an t mli after the host has asserted hstrobe and stop and t h e devi ce has negat e d dm arq and ddm ardy-, and no sooner t h an t dvs after placing the result of its crc calculation on dd (15:0). 10) the devi ce shal l l a t c h t h e host ' s c rc dat a from dd (15: 0) on t h e negat i ng edge of dm ack-.
c141-e110-02en 5 - 92 11) the device shall com p are the crc data received from the host with the results of its own crc calculation. if a m i scom pare error occurs during one or m o re ultra dma bursts for any one com m a nd, at the end of the com m a nd, the device shall report the first error that occurred (see 5.5.5). 1 2 ) the devi ce shal l rel ease ddm ardy- wi t h i n t iordyz aft e r t h e host has negat e d dm ack-. 1 3 ) th e h o s t sh all n e ith er n e g a te sto p n o r h s tro be u n til at least t ack aft e r negat i ng dm ack-. 14) the host shall not assert diow -, cs0-, cs1-, da2, da1, or da0 until at least t ack after negat i ng dm ack. 5.5.5 u l tra dma crc rul e s the following is a list of rules for calculating crc, determ ining if a crc error has occurred duri ng an ul t ra dm a burst , and report i ng any error t h at occurs at t h e end of a com m a nd. a) both the host and the device shall have a 16-bit crc calculation function. b) both the host and the device shall calculate a crc value for each ultra dma burst. c) th e crc fu n c tio n in th e h o st an d th e d e v i ce sh all b e in itialized w ith a seed o f 4 a ba h at th e begi nni ng of an ul t ra dm a burst before any dat a i s t ransferred. d) for each strobe transition used for data transfer, both the host and the device shall calcu late a n e w crc v a lu e b y ap p lyin g th e crc p o lyn o m ial to th e cu rren t v a lu e o f th eir individual crc functions and the word being transferred. crc is not calculated for the return of strobe t o t h e assert ed st at e aft e r t h e ul t r a dm a burst t e rm i n at i on request has been acknowl edged. e) at the end of any ultra dma burst the host shall send the results of its crc calculation funct i on t o t h e devi ce on dd (15: 0) wi t h t h e negat i on of dm ack-. f) the device shall then com p are the crc data from the host with the calculated value in its own crc calculation function. if the two values do not m a tch, the device shall save the error and report i t at t h e end of t h e com m a nd. a subsequent ul t r a dm a burst for t h e sam e com m and that does not have a crc error shall not clear an error saved from a previous ultra dma burst i n t h e sam e com m a nd. if a m i scom pare error occurs duri ng one or m o re ul t r a dm a burst s for any one com m a nd, at the end of the com m and, the device shall report the first error that occurred. g) for read dma or w r ite dma com m a nds: w h en a crc error is detected, it shall be reported by setting both icrc and abrt (bit 7 and bit 2 in the error register) to one. icrc is defined as the "interface crc error" bit. the host shall respond to this error by re-issuing the com m a nd. h) a host m a y send ext ra dat a words on t h e l a st ul t ra dm a burst of a dat a out com m a nd. if a device determ ines that all data has been transferred for a com m a nd, the device shall term inate the burst. a device m a y have already received m o re data words than were required for the com m a nd. these extra words are used by both the host and the device to calculate the crc, but , on an ul t ra dm a dat a out burst , t h e ext ra words shal l be di scarded by t h e devi ce.
c141-e110-02en 5 - 93 i) the crc generator polynom ial is : g (x) = x16 + x12 + x5 + 1. note: since no bit clock is available, the recom m ended approach for calculating crc is to use a word cl ock deri ved from t h e bus st robe. the com b i n at i onal l ogi c shall t h en be equivalent to shifting sixteen bits serially through the generator polynom ial where dd0 is shi ft e d i n fi rst and dd15 i s shi ft e d i n l a st . 5.5.6 series termination required for ultra dma series t e rm i n at i on resist ors are requi red at bot h t h e host and t h e devi ce for operat i on i n any of t h e ul t r a dm a m odes. the fol l owi ng t a bl e descri bes recom m ended val u es for seri es t e rm i n at i on at t h e host and t h e devi ce. table 5.16 recommended series termination for ultra dma sig n al h o st term in ation d ev ice term in ation dior-:hdmardy-:hstrobe 22 ohm 82 ohm diow-:stop 22 ohm 82 ohm cs0-, cs1- 33 ohm 82 ohm da0, da1, da2 33 ohm 82 ohm dm ack- 22 ohm 82 ohm dd15 t h rough dd0 33 ohm 33 ohm dm arq 82 ohm 22 ohm intrq 82 ohm 22 ohm iordy: ddm ardy-: d strobe 82 ohm 22 ohm reset- 33 ohm 82 ohm n o t e: o n ly th o s e sig n als req u i rin g term in atio n are listed in th is tab l e. if a sig n al is not l i s t e d, seri es t e rm i n at i on i s not requi red for operat i on i n an ul t ra dm a m ode. for si gnals also requi ri ng a pul l - up or pul l - down resi st or at t h e host see fi gure 5.7. figure 5.7 ultra dma termination with pull-up or pull-down vcc
c141-e110-02en 5 - 94 5 . 6 timing 5.6.1 pio data transfer fi gure 5.8 shows of t h e dat a t r ansfer t i m i ng bet w een t h e devi ce and t h e host syst em . t6 t1 2 t1 1 t1 0 t5 t4 t3 t9 t2 i t2 t1 t0 ad d r e sse s io r d y r e ad d ata dd0 -dd1 5 w r ite d ata dd0 -dd1 5 di or -/ di ow - s ymbo l ti m i ng param e t e r m i n . m ax. uni t t0 cycle tim e 1 2 0 n s t 1 dat a regi st er selection setup time for dior-/diow- 25 ns t 2 pul s e wi dt h of dior-/diow- 70 ns t 2 i r ecovery t i me of dior-/diow- 25 ns t 3 dat a set up t ime for diow- 20 ns t 4 dat a hol d t ime for diow- 10 ns t5 tim e from dior- assertion to read data available 50 ns t 6 dat a hol d t ime for dior- 5 ns t 9 dat a regi st er selection hold time for dior-/diow- 10 ns t 1 0 t i m e from dior-/diow- assertion to iordy "low" level 35 ns t1 1 t im e fro m validity of read data to iordy "high" level 0 ns t 1 2 p ul se wi dt h of iordy 1,250 ns figure 5.8 pio data transfer timing
c141-e110-02en 5 - 95 5.6.2 m ultiword data transfer figure 5.9 shows the m u ltiword dma data transfer tim ing between the device and the host system . tf te th tg tj td ti tc t0 read data dd0-dd15 w r ite d ata dd0 - dd1 5 di or - / di ow - dmac k- dmar q tk s y m b o l ti m i ng param e t e r m i n . m ax. unit t0 cycle tim e 1 2 0 ns t c del a y t i m e from dm ack assert i on t o dm arq negat i o n 35 ns t d pul s e wi dt h of dior-/ diow- 70 ns t e dat a set up t i m e for dior- 50 ns t f dat a hol d t i m e for dior- 5 ns t g dat a set up t i m e for diow- 20 ns t h dat a hol d t i m e for diow- 10 ns t i dm ack set up t i m e for dior-/ diow- 0 ns t j dm ack hol d t i m e for dior-/ diow- 5 ns t k cont i nuous t i m e of hi gh l e vel for dior-/ diow- 25 ns figure 5.9 multiword dma data transfer timing (mode 2)
c141-e110-02en 5 - 96 5.6.3 u l tra dma data transfer fi gures 5.10 t h rough 5.19 defi ne t h e ti m i ngs associ at ed wi t h all phases of ul t r a dm a burst s. table 5.16 contains the values for the tim ings for each of the ultra dma modes. 5.6.3.1 ini ti ati n g an ul tra dma data i n burst 5.6.3.2 contains the values for the tim ings for each of the ultra dma modes. note: the defi ni t i ons for t h e stop, hdm ardy- and dstrobe- si gnal l i n es are not i n effect u n til d m a r q an d d m a c k - are asserted . fi gure 5.10 ini ti a ti ng an ul tra dma data i n burst dmarq ( device ) dmack- ( host ) stop ( host ) hdmardy- ( host ) dstrobe (device) dd (15:0) da0, da1, da2, c s 0-,c s1- t ui t env t fs t env t za d t fs t zad t dvh t az t ziordy t ac k t ac k t ack t vds t dzfs t zfs
c141-e110-02en 5 - 97 5.6.3.2 u ltra dma data burst timing requirements table 5.17 ultra dma data burst timing requirements (1 of 2) name mode 0 ( in ns) mode 1 ( in ns) mode 2 ( in ns) mode 3 ( in ns) mode 4 ( in ns) mode 5 ( in ns) comment min max min max min max min max min max min max t 2c yc t y p 240 160 120 90 60 40 typical sustained average two cycle time t cyc 112 73 54 39 25 16.8 cycle time allowing for asymmetry and clock variations (from strobe edge to strobe edge) t 2c yc 230 153 115 86 57 38 two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of strobe) t ds 15 10 7 7 5 4 data setup time at recipient (from data valid until strobe edge) (*2), (*5) t dh 5 5 5 5 5 4.6 data hold time at recipient (from strobe edge until data may become invalid) (*2), (*5) t dvs 70 48 31 20 6.7 4.8 data valid setup time at sender (from data valid until strobe edge) (*3) t dvh 6.2 6 .2 6.2 6.2 6.2 4.8 data valid hold time at sender (from strobe edge until data may become invalid) (*3) t cs 15 10 7 7 5 5 crc word setup time at device (*2) t ch 5 5 5 5 5 5 crc word hold time device (*2) t cvs 70 48 31 20 6.7 10 crc word valid setup time at host (from crc valid until dmack- negation) (*3) t cvh 6.2 6 .2 6.2 6.2 6.2 10 crc word valid hold time at sender (from dmack-negation until crc may become invalid) (*3) t zf s 0 0 0 0 0 35 time from strobe output released-to-driving until the first transition of critical timing t dz fs 70 48 31 20 6.7 25 time from data output released-to- driving until the first transition of critical timing t fs 230 200 170 130 120 90 first strobe time (for device to first negate dstrobe from stop during a data in burst) t li 0 150 0 150 0 150 0 100 0 100 0 75 limited interlock time (*1) t ml i 20 20 20 20 20 20 interlock time with minimum (*1) t ui 0 0 0 0 0 0 unlimited interlock time (*1)
c141-e110-02en 5 - 98 table 5.17 ultra dma data burst timing requirements (2 of 2) mode 0 ( in ns) mode 1 ( in ns) mode 2 ( in ns) mode 3 ( in ns) mode 4 ( in ns) mode 5 ( in ns) name min max min max min max min max min max min max comment t az 10 10 10 10 10 10 maximum time allowed for output drivers to release (from asserted or negated) t zah 20 20 20 20 20 20 minimum delay time required for output t zad 0 0 0 0 0 0 drivers to assert or negate (from released) t env 20 70 20 70 20 70 20 55 20 55 20 50 envelope time (from dmack- to stop and hdmardy- during data in burst initiation and from dmack to stop during data out burst initiation) t rfs 75 70 60 60 60 50 ready-to-final-strobe time (no strobe edges shall be sent this long after negation of dmardy-) t rp 160 125 100 100 100 85 ready-to-pause time (that recipient shall wait to pause after negating dmardy-) t iordyz 20 20 20 20 20 20 maximum time before releasing iordy t z i ordy 0 0 0 0 0 0 minimum time before driving iordy (*4) t ac k 20 20 20 20 20 20 setup and hold times for dmack- (before assertion or negation) t ss 50 50 50 50 50 50 time from strobe edge to negation of dmarq or assertion of stop (when sender terminates a burst) *1: except for som e instances of t ml i that apply to host signals only, the param eters t ui, t ml i and t li indicate sender-to-recipient or recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a s ignal before proceeding. t ui is an unlim ited interlock that has no m a xim u m tim e value. t ml i is a lim ited tim e-out that has a defined m i nim u m . t li is a lim ited tim e-out that has a defined m a xim u m . *2: 80-conductor cabling shall be required in order to m eet setup (t ds , t cs ) and hold ( t dh , t ch ) tim es in m odes greater than 2. *3: t i m i ng for t dvs , t dvh , t cvs and t cvh shall be m et for lum p ed capacitive loads of 15 and 40 pf at the connector where all signals (data and strobe) have the sam e capacitive load value. due to reflections on the cable, the m easurem ent of these tim ings is not vali d in a norm ally functioning system . *4: for all m odes the param eter t z i ordy m ay be greater than t env due to the fact that the host has a pull up on iordy- giving it a known state when not actively driven. *5: the param eters t ds , and t dh for m ode 5 is defined for a recipient at the end of the cable only in a configuration with one device at the end of the cable. note: all tim ing m easurem ent switching points (low to high and high to low) shall be taken at 1.5v.
c141-e110-02en 5 - 99 table 5.18 ultra dma sender and recipient timing requirements mode 0 ( in ns) mode 1 ( in ns) mode 2 ( in ns) mode 3 ( in ns) mode 4 ( in ns) mode 5 ( in ns) name min max min max min max min max min max min max comment t dsic 14.7 9 .7 6.8 6 .8 4.8 2 .3 recipient ic data setup tim e (from data valid until strobe edge) ( *1) t dhic 4.8 4 .8 4.8 4 .8 4.8 2 .8 recipient ic data hold tim e (from strobe edge until data m a y become invalid) (*1) t dvsic 72.9 50.9 33.9 22.6 9 .5 6 sender ic data valid setup tim e (from data valid until strobe edge) ( *2) t dvhic 9999 96 s e n d e r i c d ata valid hold tim e (from strobe edge until data m a y becom e invalid) (*2) *1: the correct data value shall be captured by the recipient given input data with a slew rate of 0.4 v/ns rising and falling and the input strobe with a slew rate of 0.4 v/ns rising and falling at t dsi c and t dhi c tim ing ( a s m easur ed thr ough 1. 5v) . *2: the param eters t dvsi c and t dvhi c shall be m et for lum p ed capacitive loads of 15 and 40 pf at the ic where all signals have the sam e capacitive load value. noise that m a y couple onto the output signals from external sources in a norm ally functioning system has not been included in these values. note: all timing measurement switching points (low to high and high to low) shall be taken at 1.5v.
c141-e110-02en 5 - 100 5.6.3.3 sustai n ed ul tra dma data i n burst 5.6.3.2 contains the values for the tim ings for each of the ultra dma modes. note: dd (15: 0) and dstrobe si gnals are shown at bot h t h e host and t h e device t o em phasi ze t h at cab le settin g tim e as w e ll as cab le p r o p a g a tio n d e lay sh all n o t allo w th e d a ta sig n a ls to b e co n s id ered stab le at th e h o st u n til so m e tim e after th ey are d r iv en b y th e d ev i ce. fi gure 5.11 sustai ned ul tra dma data i n burst dstrobe at device dd(15:0) at device dstrobe at host dd(15:0) at host t 2cyc t cyc t dvs t dvsic t dvh t dvhic t ds t dsic t dh t dhic t 2cyc t cyc t dvs t dvsic t dvh t dvhic t dh t dhic t dh t dhic t dvh t dvhic t ds t dsic
c141-e110-02en 5 - 101 5.6.3.4 h ost pausi n g an ul tra dma data i n burst 5.6.3.2 contains the values for the tim ings for each of the ultra dma modes. notes: 1) the host m a y assert stop t o request t e rm i n at i on of t h e ul t r a dm a burst no sooner t h an t rp aft e r hdm ardy- i s negat e d. 2) after negating hdmardy-, the host m a y receive zero, one, two or three m o re data words from t h e devi ce. fi gure 5.12 host pausi n g an ul tra dma data i n burst t rp t rfs dmarq (device) dmack- (host) stop (host) hdmardy- (host) dstrobe (device) dd(15:0) (device)
c141-e110-02en 5 - 102 5.6.3.5 d evice terminating an ultra dma data in burst 5.6.3.2 contains the values for the tim ings for each of the ultra dma modes. note: the defi ni t i ons for t h e stop, hdm ardy- and dstrobe si gnal l i n es are no l onger i n effect aft e r dm arq and dm ack- are negat e d. figure 5.13 device terminating an ultra dma data in burst dmarq (device) dmack- (host) dd(15:0) hdmardy- (host) dstrobe (device) stop (host) da0, da1, da2, cs0-, cs1- t mli t li t li t li t ack t ack t iordyz t ss t zah t az t cvs t cvh crc t ack
c141-e110-02en 5 - 103 5.6.3.6 h ost terminating an ultra dma data in burst 5.6.3.2 contains the values for the tim ings for each of the ultra dma modes. note: the defi ni t i ons for t h e stop, hdm ardy- and dstrobe si gnal l i n es are no l onger i n effect aft e r dm arq and dm ack- are negat e d. figure 5.14 host terminating an ultra dma data in burst dmarq (device) t li t mli t rp t zah t az t rfs t li t mli t c vs t cv h t ack t ack t ack t iordyz crc da0, da1, da2, cs0, cs1 dmack- (host) stop (host) hdmardy- (host) dstrobe (device) dd(15:0)
c141-e110-02en 5 - 104 5.6.3.7 i ni ti ati n g an ul tra dma data out burst 5.6.3.2 contains the values for the tim ings for each of the ultra dma modes. note: the defini t i ons for t h e stop, ddm ardy- and hstrobe si gnal l i n es are not i n effect unt i l dm arq and dm ack- are assert ed. fi gure 5.15 ini ti a ti ng an ul tra dma data out burst dmarq (device) dmack- (host) stop (host) ddmardy- (device) hstrobe ( host ) dd(15:0) (host) da0, da1, da2 cs0- , cs1- t ui t ack t env t ziordy t ui t li t ac k t ack t dvh t dvs t dzfs
c141-e110-02en 5 - 105 5.6.3.8 sustai n ed ul tra dma data out burst 5.6.3.2 contains the values for the tim ings for each of the ultra dma modes. note: dd (15: 0) and hstrobe si gnals are shown at bot h t h e devi ce and t h e host t o em phasi ze t h at cab le settin g tim e as w e ll as cab le p r o p a g a tio n d e lay sh all n o t allo w th e d a ta sig n a ls to b e co n s id ered stab le at th e d ev i ce u n til so m e tim e after th ey are d r iv en b y th e h o st. fi gure 5.16 sustai n ed ul tra dma data out burst hstrobe at host hstrobe at device dd(15:0) at host dd(15:0) at device t 2cyc t cyc t cyc t 2cyc t dvh t dvhic t dvs t dvsic t dvs t dvsic t dvh t dvhic t dh t dhic t ds t dsic t dh t dhic t ds t dsic t dh t dhic t dvh t dvhic
c141-e110-02en 5 - 106 5.6.3.9 d evi ce pausi n g an ul tra dma data out burst 5.6.3.2 contains the values for the tim ings for each of the ultra dma modes. notes: 1) the device m a y negat e dm arq t o request t e rm i n at i on of t h e ul t r a dm a burst no sooner t h an t rp aft e r ddm ardy- i s negat e d. 2) after negating ddmardy-, the device m a y receive zero, one two or three m o re data words from t h e host . fi gure 5.17 devi ce pausi n g an ul tra dma data out burst dmarq (device) dmack- (host) stop (host) ddmardy- (device) hstrobe (host) dd(15:0) (host) t rp t rfs
c141-e110-02en 5 - 107 5.6.3.10 host terminating an ultra dma data out burst 5.6.3.2 contains the values for the tim ings for each of the ultra dma modes. note: the defi ni t i ons for t h e stop, ddm ardy- and hstrobe si gnal l i n es are no l onger i n effect aft e r dm arq and dm ack- are negat e d. figure 5.18 host terminating an ultra dma data out burst dmarq (device) dmack- (host) stop (host) ddmardy- (device) hstrobe (host) dd(15:0) (host) t li t li t ss t li t mli t ack t iordyz t ack t ack t cvh t cvs crc da0, da1, da2 cs0-, cs1-
c141-e110-02en 5 - 108 5.6.3.11 device terminating an ultra dma data in burst 5.6.3.2 contains the values for the tim ings for each of the ultra dma modes. note: the defi ni t i ons for t h e stop, ddm ardy- and hstrobe si gnal l i n es are no l onger i n effect aft e r dm arq and dm ack- are negat e d. figure 5.19 device terminating an ultra dma data out burst dmarq (device) dmack- (host) stop (host) ddmardy- (device) hstrobe (host) dd(15:0) (host) da0, da1, da2, cs0-, cs1- t li t li t rp t rfs t mli t mli t c vs t c vh t iordyz t ack t ack t ack crc
c141-e110-02en 5 - 109 5.6.4 p ow er-on and reset fi gure 5.20 shows power-on and reset (hardware and soft ware reset ) ti m i ng. (1) only m a ster device is present * 1: reset means including power-on-reset, hardware reset (reset-), and software reset. cle a r r e s e t *1 tp tn tm bs y dasp- po w e r - o n r es et- s o f t w a re re s e t (2) m aster and slave devices are present (2-drives configuration) tp cl e a r r e s e t [ s l a v e d ev i ce] [ m as te r d e v ic e ] tn dasp- pdi ag- bs y bs y dasp- tq tr ts s y m b o l ti m i ng param e t e r m i n . m ax. uni t t m pul s e width of reset- 25 m s t n ti m e from reset- negat i on t o bsy set 400 ns t p ti m e from reset- negation to dasp- or diag- negation 1 ms t q sel f-di agnostics execution time 30 s t r ti m e from reset- negation to dasp- assertion (slave device) 400 ms t s durat i on of dasp- assertion 31 s fi gure 5.20 pow er-on reset ti mi ng
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c141-e110-02en 6 - 1 chapter 6 opera t ions 6.1 d evi ce response to the reset 6.2 a ddress transl ati o n 6.3 pow er save 6.4 d efect management 6.5 r ead-ahead cache 6.6 wri te cache 6.1 d evi ce response to the reset thi s secti on descri bes how t h e pdiag- and dasp- si gnals responds when t h e power of t h e idd is turned on or the idd receives a reset or diagnostic com m a nd.
c141-e110-02en 6 - 2 6.1.1 r esponse to power-on aft e r t h e m a st er devi ce (devi ce 0) rel eases i t s own power-on reset st at e, t h e m a st er devi ce shal l check a dasp- si gnal for up t o 450 m s t o confi r m presence of a sl ave devi ce (devi ce 1). the m a st er devi ce recogni zes presence of t h e sl ave devi ce when i t confi r m s assert i on of t h e dasp- signal. then, the m a ster device checks a pdiag- signal to see if the slave device has successfully com p l e t e d t h e power-on di agnost i c s. if t h e m a st er devi ce cannot confi r m assert i on of t h e dasp- si gnal wi t h i n 450 m s, t h e m a st er device recogni zes t h at no sl ave devi ce i s connect ed. aft e r t h e sl ave devi ce (devi ce 1) rel eases i t s own power-on reset st at e, t h e sl ave device shall report i t s presence and t h e resul t of power-on di agnost i c s to t h e m a st er devi ce as descri bed bel ow: dasp- signal: asserted within 400 m s, and negated after the first com m and is received from t h e host or wi t h i n 31 seconds or aft e r execut i ng software reset , whi ch ever com e s first. pdiag- si gnal : negat e d wi t h i n 1 m s and assert ed wi t h i n 30 seconds, t h en negat e d wi t h i n 31 seconds. max. 31 sec. max. 400 m s . max. 31 sec. max. 30 sec. max. 1 m s . if p r esence of a slav e d e vic e is con f irm e d, pd i a g - is chec ked for up t o 31 seconds. checks dasp- for up t o 450 m s . dasp- pdiag- bsy bit powe r on re s e t - stat u s r e g. bsy bit powe r on re s et - slave device master dev i ce power on figure 6.1 response to power-on
c141-e110-02en 6 - 3 6.1.2 r esponse to hardware reset response to reset- (hardware reset through the interface) is sim ilar to the power-on reset. upon receipt of hardware reset, the m a ster device checks a dasp- signal for up to 450 m s to confi r m presence of a sl ave devi ce. the m a st er devi ce recogni zes t h e presence of t h e sl ave devi ce when i t confi r m s assert i on of t h e dasp- si gnal. then t h e m a st er devi ce checks a pdiag- si gnal to see if the slave device has successfully com p leted the self-diagnostics. if t h e m a st er devi ce cannot confi r m assert i on of t h e dasp- si gnal wi t h i n 450 m s, t h e m a st er device recogni zes t h at no sl ave devi ce i s connect ed. after the slave device receives the hardware reset, the slave device shall report its presence and t h e resul t of t h e sel f-dia gnost i c s to t h e m a st er devi ce as descri bed bel ow: dasp- signal: asserted within 400 m s, and negated after the first com m and is received from t h e host or wi t h i n 31 seconds or aft e r execut i ng software reset , whi ch ever com e s first. pdiag- si gnal : negat e d wi t h i n 1 m s and assert ed wi t h i n 30 seconds, t h en negat e d wi t h i n 31 seconds ma x. 31 s e c . ma x. 400 m s . ma x. 31 s e c . ma x. 30 s e c . ma x. 1 ms. i f p r es en ce o f a s l a v e d ev i ce i s c o n f i r m e d, p d ia g- i s c h e c ke d f o r up to 31 s e c o n ds. ch e c ks d a s p - f o r up to 450 m s . dasp- pdiag- bs y bi t re s e t - st a t u s r e g . bs y bi t s l a v e d e vi ce m a s t er d e vi ce figure 6.2 response to hardware reset
c141-e110-02en 6 - 4 6.1.3 r esponse to software reset the m a ster device does not check the dasp- signal for a software reset. if a slave device is present , t h e m a st er device checks t h e pdiag- si gnal for up t o 31 seconds t o see i f t h e sl ave device has com p leted the self-diagnosis successfully. after the slave device receives the software reset, the slave device shall report its presence and the resul t of t h e sel f-dia gnost i c s to t h e m a st er devi ce as descri bed bel ow: pdiag- si gnal : negat e d wi t h i n 1 m s and assert ed wi t h i n 30 seconds t h en negat e d wi t h i n 31 seconds. when t h e idd i s set t o a sl ave devi ce, t h e idd assert s t h e dasp- si gnal when negat i ng t h e pdiag- si gnal, and negat e s th e dasp- si gnal when assert i ng t h e pdiag- si gnal. ma x. 31 s e c . ma x. 30 s e c . ma x. 1 ms. i f the sla v e d e v i c e i s p r e s et , d a s p - i s ch eck e d fo r u p t o 31 s e c o n d s. dasp- pdiag- bs y bi t x"00" x' 3 f 6' r e g. x"0c" o r x"04 " st a t u s r e g. bs y bi t s l a v e d e vi ce m a s t er d e vi ce figure 6.3 response to software reset
c141-e110-02en 6 - 5 6.1.4 r esponse to diagnostic command w h en the m a ster device receives an execute device diagnostic com m a nd and the slave device i s present , t h e m a st er devi ce checks t h e pdiag- si gnal for up t o 6 seconds t o see i f t h e slave device has com p leted the self-diagnosis successfully. the m a st er devi ce does not check t h e dasp- si gnal. after the slave device receives the execute device diagnostic com m and, it shall report t h e resul t of t h e sel f-dia gnost i c s to t h e m a st er devi ce as descri bed bel ow: pdiag- si gnal : negat e d wi t h i n 1 m s and assert ed wi t h i n 5 seconds t h en negat e d wi t h i n 6 seconds. when t h e idd i s set t o a sl ave devi ce, t h e idd assert s t h e dasp- si gnal when negat i ng t h e pdiag- si gnal, and negat e s th e dasp- si gnal when assert i ng t h e pdiag- si gnal. ma x. 6 s e c . ma x. 5 s e c . ma x. 1 ms. if t h e slave de v i c e i s pr e s e t , das p - s i gn a l i s c h e c ke d f o r u p t o 6 se co n d s. dasp- pdiag- bs y bi t x' 1 f 7' r e g. wr i t e st a t u s r e g . bs y bi t s l a v e d e vi ce m a s t er d e vi ce figure 6.4 response to diagnostic command
c141-e110-02en 6 - 6 6.2 a ddress transl ati o n w h en the idd receives any com m a nd which involves access to the disk m e dium , the idd always im plem ents the address translation from the logical address (a host-specified address) to the phy si cal address (l ogi cal t o phy si cal address t r anslat i on). fol l owi ng subsect i ons expl ai ns t h e chs t r anslat i on m ode. 6.2.1 d efault parameters in the logical to physical address translation, the logical cylinder, head, and sector addresses are t r anslat ed t o t h e phy si cal cy l i nder, head, and sect or addresses based on t h e num ber of heads and the num ber of sectors per track which are specified with an initialize device parameters com m a nd. this is called as the current translation m ode. if t h e num ber of heads and t h e num ber of sect ors are not speci fi ed wi t h an initialize device parameters com m a nd, the default values listed in table 6.1 are used. this is called as the default t r ansl at i on m ode. the param e t e rs i n tabl e 6.1 are cal l e d bios speci fi cat i on. table 6.1 d efault parameters param e ters (logical) formatted cap acity (mb) number of cy linders number of heads n umber of sectors/track m p g3102at 10,248 16,383 16 63 m p g3153at 15,371 -- - m p g3204at 20,496 -- - m p g3307at 30,743 -- - m p g3409at 40,992 -- - as long as the form atted capacity of the idd does not exceed the value shown on table 6.1, the host can freel y speci fy t h e num ber of cy l i nders, heads, and sect ors per t r ack. generally, the device recognizes the num ber of heads and sectors per track with the initialize device parameter com m a nd. however, it cannot recognizes the num ber of cylinders. in other words, there is no way for the device to recognize a host access area on logical cylinders. thus the host should m a nage cylinder access to the device. the host can specify a logical address freely within an area where an address can be specified (within the specified num ber of cylinders, heads, and sectors per track) in the current translation m ode. the host can read an addressable param e ter inform ation from the device by the identify device com m and (words 54 to 56).
c141-e110-02en 6 - 7 6.2.2 l ogi cal address (1) c hs m ode logical address assignm ent st art s from phy si cal cy l i nder (pc) 0, phy si cal head (ph) 0, and phy si cal sector (ps) 1 and i s assigned by cal cul a t i ng t h e num ber of sect ors per t r ack whi ch i s specified by the initialize device parameters com m a nd. the head address is advanced at the subsequent sector from the last sector of the current physical head address. the first physical sector of the subsequent physical sector is the consecutive logical sector from the last sector of the current physical sector. fi gure 6.5 shows an exam pl e (assum i ng t h ere i s no t r ack skew). ls 63 lh2 lh1 lh0 ls 2 ls 1 ls 1 798 797 796 190 189 64 63 62 3 2 34 33 1 1 127 126 p hy s ical sector p hy s ical sector ex: zone 0 phy s ical parameter - phy s ical sector: 1 to 798 (for the rest, 2 spare sectors) specification of initialize device parameters com m a nd - logical head: lh=0 to 15 - logical sector: ls =1 to 63 p hy s ical cy linder 0 p hy s ical head 1 p hy s ical cy linder 0 p hy s ical head 0 ls 63 ls 1 ls 63 ls 1 ls 30 ls 29 ls 28 .. .. .. .. .. .. .. .. ls 63 ls 31 ls 1 ls 63 ls 1 ls 63 ls 1 ls 1 ls 63 .. .. .. .. .. .. .. .. .... .... .... lh14 lh13 lh15 lh16 lh1 97 160 159 96 223 222 798 797 fi gure 6.5 a ddress transl ati o n (exampl e i n chs mode)
c141-e110-02en 6 - 8 (2) l ba m ode logical address assignm ent i n t h e lba m ode st art s from phy si cal cy l i nder 0, phy si cal head 0, and phy si cal sector 1. the l ogi cal address i s advanced at t h e subsequent sect or from t h e l a st sect or of the current track. the first physical sector of the subsequent physical track is the consecutive logical sector from the last sector of the current physical track. fi gure 6.6 shows an exam pl e of (assum i ng t h ere i s no t r ack skew). lb a 2 lb a 1 lb a 797 lb a 796 lb a 795 796 795 lb a 794 lb a 0 3 2 1 p h y s i cal sect o r e x : zone 0 p h y s i cal p a ram e t e r - p h y s ic a l se c t or: 1 to 798 p h y s i cal cy l i n d e r 0 p h y s i cal h ead 0 ...................... ...................... lb a 1595 lb a 1594 lb a 1593 lb a 1592 3 2 1 p h y s i cal cy l i n d e r 0 p h y s i cal h ead 1 ...................... ...................... lb a 800 lb a 799 lb a 798 798 797 796 795 798 797 fi gure 6.6 a ddress transl ati o n (exampl e in lba mode) 6.3 pow er save the host can change t h e power consum pt i on st at e of t h e devi ce by i ssuing a power com m a nd t o the device. 6.3.1 pow er save mode there are four t y p es of power consum pt i on st at e of t h e device i n cl udi ng act i v e m ode where al l circuits are active. in the power save m ode, power supplying to the part of the circuit is turned off. there are three t y p es of power save m odes: idle m ode st andby m ode sleep m ode (1 ) a ctive m o d e in t h i s m ode, al l t h e el ect ri c ci rcuit i n t h e devi ce are act i v e or t h e device i s under seek, read or wri t e operat i on.
c141-e110-02en 6 - 9 a device enters the active m ode under the following conditions: a com m a nd wi t h seek or wri t e or read i s i ssued. (2) idl e m ode in th i s m ode, ci rcuit s on t h e devi ce is set t o power save mode. the device enters the idle m ode under the following conditions: a idle or idle im m ediate com m a nd i s i ssued i n t h e act i v e or st andby m ode. w h en o n e o f fo llo w i n g co m m an d is issu ed , th e co m m an d is ex ecu ted n o r m ally an d th e d ev i ce is still stayed in th e id le m o d e . C r eset (hardware or software) C i dle com m a nd C i dle immediate com m and C a com m a nd wi t hout seek or wri t e or read i s i ssued. (3) st a ndby m ode in t h i s m ode, t h e vcm circuit i s t u rned off and t h e spi ndl e m o t o r is stopped. the device can receive com m a nds through the interface. however if a com m and with disk access i s i ssued, response t i m e t o t h e com m a nd under t h e st andby m ode t a kes l onger t h an t h e act i v e or idle m ode because the access to the disk m e dium cannot be m a de im m e diately. the drive enters the standby m ode under the following conditions: a standby or standby im m ediate com m a nd i s i ssued i n t h e act i v e or i d l e m ode. when aut o m a t i c power down sequence i s enabl e d, t h e ti m er has el apsed. a reset is issu ed in th e sleep m o d e. w h en o n e o f fo llo w i n g co m m an d s is issu ed , th e co m m an d is ex ecu ted n o r m ally an d th e d ev i ce is still stayed in the standby m ode. reset (hardware or software) standby com m a nd standby im m ediate com m a nd a com m a nd wi t hout seek or wri t e or read i s i ssued check power m ode com m a nd
c141-e110-02en 6 - 10 (4) sleep m ode the power consum pt i on of t h e dri v e i s m i ni m a l i n t h i s m ode. the dri v e ent e rs onl y t h e st andby m ode from t h e sl eep m ode. the onl y m e t hod t o ret u rn from t h e st andby m ode i s t o execut e a software or hardware reset. the drive enters the sleep m ode under the following condition: a sleep com m a nd is issued. issued com m a nds are i nval i d (i gnored) i n t h i s m ode. 6.3.2 power commands the fol l owi ng com m a nds are avai l a bl e as power com m ands. idle idle im m ediate standby standby im m ediate sleep check power m ode 6.4 d efect management defective sectors of which the m e dium defect location is registered in the system space are replaced with spare sectors in the form atting at the factory shipm e nt. all the user space area are form atted at shipm e nt from the factory based on the default param e ters l i st e d i n tabl e 6.1.
c141-e110-02en 6 - 11 6.4.1 spare area fol l owi ng t wo t y p es of spare area are provided i n t h e user space. 1) spare sector for sector slip: used for alternating defective sectors at form atting in shipm e nt (128 sectors/32 cylinders) 2) spare cylinder for alternative assignm ent: u sed b y au to m atic altern ative assig n m en t. (4 cylind er/dr iv e) 6.4.2 a lternating defective sectors the t wo al t e rnati ng m e t hods descri bed bel ow are avai l a bl e: (1) sector sl i p processi ng a defect i v e sector i s not used and i s ski pped and a l ogi cal sect or address i s assi gned t o t h e subsequent norm a l sector (physically adjacent sector to the defective sector). w h en defective sector is present, the sector slip processing is perform ed in the form atting. figure 6.7 shows an exam ple where (physical) sector 5 is defective on head 0 in cylinder 0. 2 1 index head 0 defec t ive sec t or if an access requ est to sector 5 is specified, the device accesses physical sector 6 in stead of secto r 5. sector (log ical) sector (physical) cy linder 0 4 36 5 795 798 797 796 8 7 2 14 36 57 797 796 figure 6.7 s ector slip processing unused
c141-e110-02en 6 - 12 (2) a lternate cylinder assignm ent a defective sector is assigned to the spare sector in the alternate cylinder. thi s processi ng i s perform ed when a phy si cal t r ack cont ai ns t h ree or m o re defect i v e sectors, and when t h e aut o m a t i c alt e rnate processi ng i s perform ed. figure 6.8 shows an exam ple where (physical) sector 5 is detective on head 0 in cylinder 0. 57 6 4 3 1 798 797 2 index cy linder 0 head 0 head 0 already assigned defec t ive sec t or 4 alternate cy lind e rs are p r ovided for each head in zon e 13 (inner side). w he n a n ac ce ss reques t to se ctor 5 is spe c ifie d, the de vice ac ce ss es the alte rnate d s e c t or in the alternate cy linder instead of sector 5. w hen an access req uest to sectors nex t to sector 5 is specified, the d e vice seeks to cy linder 0, h ead 0, and contin ues the processin g. defective sector is assigned to u nassigned secto r . (unu sed) sector (logical) sector (physical) al te rna t e cylinder 2 14 36 7 798 797 figure 6.8 a lternate cylinder assignment (3) autom atic alternate assignm ent the device perform s the autom a tic assignm ent at following case. 1) w h en ecc correction perform ance is increased during read error retry, a read error is recovered. before autom a tic alternate assignm ent, the device perform s rewriting the corrected data to the erred sector and rereading. if no error occurs at rereading, the autom a tic alternate assignm ent is not perform ed. 2) w h en a write error occurs and the error does not recovered. 1 al t e rnat e cy l i nder i s provided in i nner si de.
c141-e110-02en 6 - 13 6.5 r ead-ahead cache after a read com m a nd which reads the data from the disk m e dium is com p leted, the read-ahead cache function reads the subsequent data blocks autom a tically and stores the data in the data buffer. w h en the next com m a nd requests to read the read-ahead data, the data can be transferred from the data buffer without accessing the disk m e dium . the host can access the data at higher speed. 6.5.1 data buffer confi g urati o n the devi ce has a 512-kb or 2,048-kb dat a buffer. the buffer i s used by di vi ded i n t o t wo and other com m a nds parts; for mpu work, for read cache of read com m ands and other com m a nds (see fi gure 6.9). for r/w com m a nd for m p u work 432 kb (442,368 bytes) 80 kb (81,920 by t e s) 512 kb (524,288 by t e s) for r/w command for m p u work 1,968 kb (2,015,232 bytes) 80 kb (81,920 by t e s) 2,048 kb (2,097,152 by t e s) fi gure 6.9 data buffer confi g urati o n the read-ahead operat i on i s perform ed at execut i on of t h e read sector(s), read multiple, or read dma command, and read-ahead data are stored in the buffer for read cache.
c141-e110-02en 6 - 14 6.5.2 cachi ng operati on the caching operation is perform ed only at receipt of the following com m a nds. the device transfers d ata fro m th e d ata b u ffer to th e h o s t system if th e fo llo w i n g d ata ex ist in th e d ata b u ffer. al l sect or dat a t o be processed by t h e com m a nd a part of dat a i n cl udi ng t h e st art i ng sect or t o be processed by t h e com m a nd w h en a p art o f d ata to b e p r o cessed ex ist in th e d ata b u ffer, th e rem ain in g d ata are read fro m th e di sk m e di um and are t r ansferred t o t h e host syst em . (1) c om m a nds that are object of caching operation the following com m a nds are object of caching operation. read sector (s) read multiple read dm a read verify (onl y sequent i a l access) w h en the caching operation is disabled by the set features com m a nd, no caching operation is perform ed. (2) d ata that are object of caching operation the following data are object of caching operation. 1) read-ahead dat a read from t h e di sk m e di um i n t h e dat a buffer aft e r com p l e t i on of t h e com m a nd that are object of caching operation. 2) dat a t r ansferred t o t h e host sy st em once by request i ng wi t h t h e com m and t h at are object of caching operation. w h en the sector data requested by the host does not finish storing in the buffer for read cache, it is not object of caching operation. and also, when the sequential hit occurs continuously, the caching data required by the host becom e s invalid. (3) i nvalidating caching data cachin g d ata in th e d ata b u ffer is in v alidated in th e fo llo w i n g case. 1 ) com m a nds other than the following com m a nds are issued (all caching data are invalidated) w r ite sector(s) read sector(s) w r ite dma read multiple w r ite multiple read dm a check power m ode 2) cachi ng operat i on i s disabled by t h e set features com m a nd. 3 ) co m m an d issu ed b y th e h o st is term in ated w ith an erro r. 4) soft reset or hard reset i s execut e d, or power i s t u rned off.
c141-e110-02en 6 - 15 6.5.3 u sage of read segment thi s subsect i on expl ai ns t h e usage of t h e read segm ent buffer at fol l owi ng cases. (1 ) miss-h it (n o h it) a l ead bl ock of t h e read-request ed dat a i s not st ored i n t h e dat a buffer. the request ed dat a i s read from the disk m e dia. 1) set s t h e host address poi nt er (hap) and t h e di sk address poi nt er (dap) t o t h e sequent i a l address to the last read segm ent. segm ent for read dap hap 2) transfers the requested data that already read to the host system with reading the requested dat a from t h e di sk m e di a. r e a d-r e que s t e d da t a s t o r es the read-requested data upto this point empty area dap hap 3) afte r readi ng t h e request ed dat a and t r ansferri ng t h e request ed dat a t o t h e host sy st em had been com p leted, the disk drive continues to read till a certain am ount of data is stored. r e a d-r e que s t e d da t a r e ad a h e a d d ata dap (s t o ppe d) ha p 4) following shows the cache enabled data for next read command. cache enabled data last lba start lba (st opped)
c141-e110-02en 6 - 16 (3 ) s eq u en tial read w h en the disk drive receives the read com m a nd that targets the sequential address to the previous read com m a nd, the disk drive tries to fill the buffer space with the read ahead data. a. sequent i a l com m a nd just aft e r non-sequent i a l com m a nd 1) at receiving the sequential read com m and, the disk drive sets the dap and hap to the sequent i a l address of t h e la st read com m a nd and reads t h e request ed dat a . e m pt y da t a m is -h it d ata 2) the disk drive transfers the requested data that is already read to the host system with readi ng t h e request ed dat a . request ed dat a dap hap mis-h it d a ta em p ty d a ta 3) aft e r com p l e t i on of t h e readi ng and t r ansferri ng t h e request ed dat a t o t h e host sy st em , the disk drive perform s the read-ahead operation continuously till a certain amount of data is stored. mis-h it d a ta request ed dat a dap hap em pty dat a read- ahead data dap hap
c141-e110-02en 6 - 17 b. sequent i a l hi t w h en the last sector address of the previous read com m a nd is sequential to the lead sector address of the received read com m a nd, the disk drive transfers the hit data in the buffer to the host system . the di sk dri v e perform s t h e read-ahead operat i on of t h e new cont i nuous dat a t o t h e em pt y area that becom e s vacant by data transfer at the sam e tim e as the disk drive starts transferring d a ta to th e h o st system . 1) in the case that the contents of buffer is as follows at receiving a read com m a nd; start lba la s t lb a da p ha p (c om pl et i o n of t ran s f erri n g requ es t e d dat a ) hit d a ta r ead- a h ead data 2) the disk drive starts the read-ahead operation to the em pty area that becom e s vacant by d a ta tran sfer at th e sam e tim e as th e d i sk d r iv e starts tran sferrin g h it d ata. dap hap h it d a ta new read-ahead dat a read-ahead data 3) aft e r com p l e t i on of dat a t r ansfer of hi t dat a , t h e di sk dri v e perform s t h e read-ahead operat i on for t h e dat a area of whi ch t h e di sk dri v e t r ansferred hi t dat a . read-ahead data dap hap
c141-e110-02en 6 - 18 (3 ) f u ll h it (h it all) all requested data are stored in the data buffer. the disk drive starts transferring the requested dat a from t h e address of whi ch t h e request ed dat a i s st ored. aft e r com p l e t i on of com m and, a previously existed cache data before the full hit reading are still kept in the buffer, and the disk drive does not perform the read-ahead operation. if the disk drive receives a full hit com m a nd whi l e perform i ng t h e read-ahead operat i o n, t h e di sk dri v e st art s t r ansferi ng t h e request ed dat a wi t hout st oppi ng t h e read-ahead operat i on. 1) in the case that the contents of the data buffer is as follows for exam ple and the previous com m a nd i s a sequent i a l read com m a nd, t h e di sk dri v e set s t h e hap t o t h e address of whi ch th e h it d ata is sto r ed . hap (set t o hi t position for data transfer) last position at previ ous read com m a nd last posi t i on at previ ous read com m and cache data fu ll h it d a ta cache data 2) the disk driv e t r ansfers t h e request ed dat a but does not perform t h e read-ahead operat i on. (s t o ppe d) hap cach e d a t a f u ll h it d ata ca ch e d a t a (4 ) p artially h i t a part of request ed dat a i n cl udi ng a l ead sect or are st ored i n t h e dat a buffer. the di sk dri v e st art s t h e dat a t r ansfer from t h e address of t h e hi t dat a correspondi ng t o t h e l ead sector of t h e request ed d ata, and read s rem ain in g req u ested d ata from th e d i sk m ed i a d i rectly. following is an exam ple of partially hit to the cache data. last lba cache data dap hap start lba
c141-e110-02en 6 - 19 1 ) th e d i sk d r iv e sets th e h a p to th e ad d r ess w h ere th e p artially h it d ata is sto r ed , an d sets th e d a p to th e ad d r ess j u st after th e p artially h it d ata. ha p dap p a r tially h it d ata l ac k d ata 2 ) th e d i sk d r iv e starts tran sferrin g p artially h it d ata an d read s lack d ata fro m th e d i sk m ed i a at th e sam e tim e. (s t opped) ha p r e quested dat a t o be t r an s f erred da p p a rtially hit d a ta l ack d a ta
c141-e110-02en 6 - 20 6.6 w ri te cache the write cache function of the drive m a kes a high speed processing in the case that data to be written by a write com m a nd is logically sequent the data of previous com m and and random write operat i on i s perform ed. w h en the drive receives a write com m and, the drive starts transferring data of sectors requested by t h e host sy st em and wri t i ng on t h e di sk m e di um . aft e r t r ansferri ng dat a of sectors request ed b y th e h o st system , th e d r iv e g en erates th e in terru p t o f co m m an d co m p lete. a l so , th e d r iv e sets t h e norm a l end st at us i n t h e st at us regist er. the dri v e cont i nues wri t i ng dat a on t h e di sk m e di um . w h en all d a ta req u e sted b y th e h o st are w r itten o n th e d i sk m e d i u m , actu a l w r ite o p e ratio n is co m p leted . the drive receives the next com m and continuously. if the received com m and is a "sequential w r ite" (d ata to b e w r itten b y a co m m an d is lo g i cally seq u en t to d ata o f p r ev io u s co m m an d ), th e drive starts data transfer and receives data of sectors requested by the host system . at this tim e, if the write operation of the previous com m a nd is still been executed, the drive continuously execut e s t h e wri t e operat i on of t h e next com m a nd from t h e sect or next t o t h e l a st sect or of t h e previ ous wri t e operat i on. thus, t h e l a t e ncy t i m e for det ect i ng a t a rget sect or of t h e next com m and is elim inated. this shortens the access tim e. the drive generates an interrupt of com m a nd com p lete after com p letion of data transfer requested by the host system as sam e as at previous com m a nd. when t h e wri t e operat i on of t h e previ ous com m and had been com p l e t e d, t h e l a t e ncy tim e occurs to search the target sector. if the received com m a nd is not a "sequential write", the drive receives data of sectors requested by the host system as sam e as "sequential write". the drive generates the interrupt of com m and com p lete after com p letion of data transfer requested by the host system . received data is processed aft e r com p l e t i on of t h e wri t e operat i on t o t h e di sk m e di um of t h e previ ous com m and. even if a hard reset or soft reset is received or the write cache function is disabled by the set features com m a nd during unwritten data is kept, the instruction is not executed until rem a ining unwritten data is written onto the disk m e dium . the drive uses a write data as a read cache data. w h en a read com m a nd is issued to the sam e address aft e r t h e wri t e com m a nd, t h e read operat i on t o t h e di sk m e di um i s not perform ed. when an error occurs duri ng t h e wri t e operat i on, t h e dri v e m a kes ret ry as m u ch as possi bl e. if t h e error cannot be recovered by ret r y , t h e dri v e st ops t h e wri t e operat i on t o t h e erred sect or, and continues the write operation from the next sector if the write data is rem a ined. (if the drive stacks a write com m and, for that the drive posts the com m a nd com p letion, next to the com m a nd t h at wri t e operat i on i s st opped by error occurrence.) aft e r an error occurs at above wri t e operat i on, t h e dri v e post s th e error st at us t o th e host sy st em at next com m a nd. (the dri v e does not execut e t h i s com m a nd, set s t h e error st at us t h at occurred at t h e wri t e operat i on, and generat e s t h e interrupt for abnorm a l end. however, when the drive receives a write com m a nd after the com p l e t i on of error processi ng, t h e dri v e post s t h e error aft e r wri t i ng t h e wri t e dat a of t h e wri t e c o mma n d . )
c141-e110-02en 6 - 21 at t h e t i m e t h at t h e dri v e has st opped t h e com m and execut i on aft e r t h e error recovery has fai l e d, the write cache function is disabled autom a tically. the releasing the disable state can be done by t h e set features com m a nd. when t h e power of t h e dri v e i s t u rned on aft e r t h e power i s turned off once, the status of the write cache function returns to the default state. the default state is write cache enable, and can be disable by the set features com m and. the write cache function is operated with the following com m a nd. w r ite sector(s) w r ite multiple w r ite dma important when t h e wri t e cache f unct i on i s enabl ed, t h e t ransf e rred dat a f rom t h e host by the write sector(s) is not completely written on the disk medi um at t h e t i m e t hat t h e i n t e rrupt of command compl et e i s generated. when the unrecoverable error occurs during the write operation, the command execution is stopped. then, when the drive receives the next command, it generates an interrupt of abnormal end. however an interrupt of abnormal end is not generated when a write automatic assignment succeeds. however, since the host may issue several write commands before the drive generates an interrupt of abnormal end, t h e host cannot recogni ze t hat t h e occurred error i s f o r whi c h command general l y . theref ore, i t i s very hard t o ret ry t h e unrecoverable write error for the host in the write cache operation generally. so, take care to use the write cache function.
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